🥇O le lua HDMI mataitu ile Raspberry Pi3 e ala ile DPI interface ma le FPGA board

O lenei vitio o loʻo faʻaalia: o le Raspberry Pi3 laupapa, faʻafesoʻotaʻi i ai e ala i le GPIO connector o le FPGA board Mars Rover2rpi (Afa o IV), lea e fesoʻotaʻi ai le mataʻitu HDMI. Ole mata'itu lona lua e feso'ota'i ile feso'ota'iga HDMI masani ole Raspberry Pi3. E galulue fa'atasi mea uma e pei o se masini mata'itu lua.

Le isi o le a ou taʻu atu ia te oe pe faʻapefea ona faʻatinoina lenei mea.

O le lauiloa Raspberry Pi3 laupapa o loʻo i ai se fesoʻotaʻiga GPIO e mafai ona e faʻafesoʻotaʻi ai kata faʻalautele eseese: sensors, LEDs, stepper motor drivers ma sili atu. O le galuega tonu o pine ta'itasi i luga o se feso'ota'iga e fa'alagolago i le fa'atulagaina o le taulaga. O le GPIO ALT2 faʻatulagaina e mafai ai e oe ona fesuiaʻi le fesoʻotaʻiga i le DPI interface mode, Faʻaali Faʻasalalauga Faʻatasi. O lo'o iai kata fa'alautele e fa'afeso'ota'i mata'itū VGA e ala i le DPI. Ae ui i lea, muamua, e le o toe tutusa le mataʻituina o le VGA e pei o le HDMI, ma lona lua, o le fesoʻotaʻiga numera e sili atu le lelei nai lo le analog. E le gata i lea, o le DAC i luga o ia laupapa faʻalautele VGA e masani lava ona faia i foliga o filifili R-2-R ma e masani lava e le sili atu i le 6 paʻu ile lanu.

I le ALT2 mode, o pine faʻafesoʻotaʻi GPIO o loʻo iai lona uiga:

O lea ua ou valiina pine RGB o le fesoʻotaʻiga mumu, lanumeamata ma le lanumoana. O isi faʻailoga taua o faailo V-SYNC ma H-SYNC, faʻapea foʻi ma CLK. Ole taimi ole uati ole CLK ole ole taimi lea e maua ai le tau ole pika ile feso'ota'iga; e fa'alagolago ile ata vitio filifilia.

Ina ia faʻafesoʻotaʻi se mataʻitusi HDMI numera, e tatau ona e puʻeina faʻailoga DPI o le atinaʻe ma faʻaliliu i faʻailoga HDMI. E mafai ona faia lenei mea, mo se faʻataʻitaʻiga, faʻaaogaina se ituaiga o laupapa FPGA. E pei ona aliali mai, o le Mars Rover2rpi laupapa e talafeagai mo nei faʻamoemoe. O le mea moni, o le filifiliga autu mo le faʻafesoʻotaʻi o lenei laupapa e ala i se faʻaoga faʻapitoa e pei o lenei:

O lenei laupapa e faʻaaogaina e faʻateleina ai le numera o ports GPIO ma faʻafesoʻotaʻi isi masini faʻapitoa i le rasipi. I le taimi lava e tasi, e 4 faʻailoga GPIO faʻatasi ai ma lenei fesoʻotaʻiga e faʻaaogaina mo faailo JTAG, ina ia mafai e le polokalame mai Raspberry ona utaina le firmware FPGA i le FPGA. Ona o lenei mea, o lenei fesoʻotaʻiga masani e le fetaui ma aʻu; 4 faʻailoga DPI e pa'ū. O le mea e laki ai, o selu fa'aopoopo i luga o le laupapa o lo'o i ai se pine e fetaui ma Raspberry. O lea e mafai ai ona ou fesuiaʻi le laupapa 90 tikeri ma faʻafesoʻotaʻi pea i laʻu rasipi:

Ioe, e tatau ona e faʻaaogaina se polokalame JTAG fafo, ae e le o se faʻafitauli.

O lo'o iai lava sina fa'afitauli. E le mafai ona fa'aoga uma pine FPGA e fai ma fa'aoga uati. E na'o ni nai pine fa'apitoa e mafai ona fa'aoga mo nei fa'amoemoe. O lea na aliali mai iinei o le faailo GPIO_0 CLK e le oʻo atu i le FPGA input, lea e mafai ona faʻaaogaina e fai ma faʻaoga FPGA uati. O lea sa tatau lava ona ou tuu se uaea se tasi i luga o le sikafu. Ou te fa'afeso'ota'i le GPIO_0 ma le fa'ailoga KEY[1] a le laupapa:

O lenei o le a ou taʻu atu ia te oe sina mea itiiti e uiga i le FPGA poloketi. O le faigata tele i le fa'atupuina o fa'ailoga HDMI o laina maualuga tele. Afai e te vaʻavaʻai i le fesoʻotaʻiga HDMI pinout, e mafai ona e vaʻaia o faailo RGB ua avea nei ma faʻailoga eseese faʻasologa:

O le faʻaogaina o se faʻailoga faʻapitoa e mafai ai e oe ona faʻafefe faʻalavelave masani masani ile laina faʻasalalau. I lenei tulaga, o le uluaʻi valu-bit code o faailo lanu taʻitasi ua liua i le 10-bit TMDS (Transition-minimized differential signaling). O se auala faʻapitoa faʻailoga e aveese ai le vaega DC mai le faʻailoga ma faʻaitiitia ai le fesuiaiga o faailo i se laina ese. Talu ai o le 10 bits ua manaʻomia nei ona tuʻuina atu i luga o le laina laina mo le tasi paita o lanu, e foliga mai o le saoasaoa o le serializer e tatau ona 10 taimi maualuga atu nai lo le pixel speed speed. Afai tatou te faia mo se faʻataʻitaʻiga le ata vitio 1280x720 60Hz, ona o le pika ole taimi ole faiga ole 74,25 MHz. O le serializer e tatau ona 742,5 MHz.

O FPGA masani, o le mea e leaga ai, e le mafai ona faia lenei mea. Ae ui i lea, o le mea e lelei ai mo i matou, o le FPGA ua fausia i totonu DDIO pine. O fa'ai'uga ia ua leva, e pei ona i ai, 2-to-1 serializers. O lona uiga, e mafai ona latou fa'aulu fa'asolosolo fa'asologa e lua i luga o le si'isi'i ma le pa'u pito o le taimi o le uati. O lona uiga i totonu o se poloketi FPGA e le mafai ona e faʻaogaina le 740 MHz, ae 370 MHz, ae e te manaʻomia le faʻaogaina o elemene DDIO i le FPGA. Ole taimi nei ole 370 MHz ua mae'a ona mafai ona ausia. Ae paga lea, 1280x720 mode o le tapulaʻa. E le mafai ona maua se iuga maualuga i la matou Afa IV FPGA fa'apipi'i i luga o le laupapa Mars Rover2rpi.

O le mea lea, i le mamanu, o le pixel input frequency CLK e alu i le PLL, lea e faʻateleina i le 5. I lenei taimi, o le R, G, B bytes ua liua i ni paipa. O le mea lea e fai e le TMDS encoder. Ole faʻailoga autu ile Verilog HDL e pei o lenei:

module hdmi(
	input wire pixclk,		// 74MHz
	input wire clk_TMDS2,	// 370MHz
	input wire hsync,
	input wire vsync,
	input wire active,
	input wire [7:0]red,
	input wire [7:0]green,
	input wire [7:0]blue,
	output wire TMDS_bh,
	output wire TMDS_bl,
	output wire TMDS_gh,
	output wire TMDS_gl,
	output wire TMDS_rh,
	output wire TMDS_rl
);

wire [9:0] TMDS_red, TMDS_green, TMDS_blue;
TMDS_encoder encode_R(.clk(pixclk), .VD(red  ), .CD({vsync,hsync}), .VDE(active), .TMDS(TMDS_red));
TMDS_encoder encode_G(.clk(pixclk), .VD(green), .CD({vsync,hsync}), .VDE(active), .TMDS(TMDS_green));
TMDS_encoder encode_B(.clk(pixclk), .VD(blue ), .CD({vsync,hsync}), .VDE(active), .TMDS(TMDS_blue));

reg [2:0] TMDS_mod5=0;  // modulus 5 counter
reg [4:0] TMDS_shift_bh=0, TMDS_shift_bl=0;
reg [4:0] TMDS_shift_gh=0, TMDS_shift_gl=0;
reg [4:0] TMDS_shift_rh=0, TMDS_shift_rl=0;

wire [4:0] TMDS_blue_l  = {TMDS_blue[9],TMDS_blue[7],TMDS_blue[5],TMDS_blue[3],TMDS_blue[1]};
wire [4:0] TMDS_blue_h  = {TMDS_blue[8],TMDS_blue[6],TMDS_blue[4],TMDS_blue[2],TMDS_blue[0]};
wire [4:0] TMDS_green_l = {TMDS_green[9],TMDS_green[7],TMDS_green[5],TMDS_green[3],TMDS_green[1]};
wire [4:0] TMDS_green_h = {TMDS_green[8],TMDS_green[6],TMDS_green[4],TMDS_green[2],TMDS_green[0]};
wire [4:0] TMDS_red_l   = {TMDS_red[9],TMDS_red[7],TMDS_red[5],TMDS_red[3],TMDS_red[1]};
wire [4:0] TMDS_red_h   = {TMDS_red[8],TMDS_red[6],TMDS_red[4],TMDS_red[2],TMDS_red[0]};

always @(posedge clk_TMDS2)
begin
	TMDS_shift_bh <= TMDS_mod5[2] ? TMDS_blue_h  : TMDS_shift_bh  [4:1];
	TMDS_shift_bl <= TMDS_mod5[2] ? TMDS_blue_l  : TMDS_shift_bl  [4:1];
	TMDS_shift_gh <= TMDS_mod5[2] ? TMDS_green_h : TMDS_shift_gh  [4:1];
	TMDS_shift_gl <= TMDS_mod5[2] ? TMDS_green_l : TMDS_shift_gl  [4:1];
	TMDS_shift_rh <= TMDS_mod5[2] ? TMDS_red_h   : TMDS_shift_rh  [4:1];
	TMDS_shift_rl <= TMDS_mod5[2] ? TMDS_red_l   : TMDS_shift_rl  [4:1];
	TMDS_mod5 <= (TMDS_mod5[2]) ? 3'd0 : TMDS_mod5+3'd1;
end

assign TMDS_bh = TMDS_shift_bh[0];
assign TMDS_bl = TMDS_shift_bl[0];
assign TMDS_gh = TMDS_shift_gh[0];
assign TMDS_gl = TMDS_shift_gl[0];
assign TMDS_rh = TMDS_shift_rh[0];
assign TMDS_rl = TMDS_shift_rl[0];

endmodule

module TMDS_encoder(
	input clk,
	input [7:0] VD,	// video data (red, green or blue)
	input [1:0] CD,	// control data
	input VDE,  	// video data enable, to choose between CD (when VDE=0) and VD (when VDE=1)
	output reg [9:0] TMDS = 0
);

wire [3:0] Nb1s = VD[0] + VD[1] + VD[2] + VD[3] + VD[4] + VD[5] + VD[6] + VD[7];
wire XNOR = (Nb1s>4'd4) || (Nb1s==4'd4 && VD[0]==1'b0);
wire [8:0] q_m = {~XNOR, q_m[6:0] ^ VD[7:1] ^ {7{XNOR}}, VD[0]};

reg [3:0] balance_acc = 0;
wire [3:0] balance = q_m[0] + q_m[1] + q_m[2] + q_m[3] + q_m[4] + q_m[5] + q_m[6] + q_m[7] - 4'd4;
wire balance_sign_eq = (balance[3] == balance_acc[3]);
wire invert_q_m = (balance==0 || balance_acc==0) ? ~q_m[8] : balance_sign_eq;
wire [3:0] balance_acc_inc = balance - ({q_m[8] ^ ~balance_sign_eq} & ~(balance==0 || balance_acc==0));
wire [3:0] balance_acc_new = invert_q_m ? balance_acc-balance_acc_inc : balance_acc+balance_acc_inc;
wire [9:0] TMDS_data = {invert_q_m, q_m[8], q_m[7:0] ^ {8{invert_q_m}}};
wire [9:0] TMDS_code = CD[1] ? (CD[0] ? 10'b1010101011 : 10'b0101010100) : (CD[0] ? 10'b0010101011 : 10'b1101010100);

always @(posedge clk) TMDS <= VDE ? TMDS_data : TMDS_code;
always @(posedge clk) balance_acc <= VDE ? balance_acc_new : 4'h0;

endmodule

Ona fafaga lea o pa'aga i le DDIO, lea e maua ai se fa'ailoga e tasi le pito i luga ma le pa'u.

DDIO lava ia e mafai ona faʻamatalaina i le Verilog code nei:

module ddio(
	input wire d0,
	input wire d1,
	input wire clk,
	output wire out
	);

reg r_d0;
reg r_d1;
always @(posedge clk)
begin
	r_d0 <= d0;
	r_d1 <= d1;
end
assign out = clk ? r_d0 : r_d1;
endmodule

Ae e foliga mai o le a le aoga i lena auala. E mana'omia lou fa'aogaina o le Alter's megafunction ALTDDIO_OUT e fa'aaga tonu ai le DDIO elemene fa'atino. O la'u poloketi e fa'aoga ai le vaega faletusi ALTDIO_OUT.

Atonu e foliga faigata uma, ae e aoga.

E mafai ona e va'ai i fa'amatalaga puna uma na tusia i le Verilog HDL iinei ile github.

O le firmware tuʻufaʻatasia mo le FPGA o loʻo faʻapipiʻiina i totonu o le pulou EPCS faʻapipiʻi i luga o le laupapa Mars Rover2rpi. O le mea lea, pe a faʻaogaina le mana i le laupapa FPGA, o le FPGA o le a amataina mai le flash memory ma amata.

O lenei e tatau ona tatou talanoa laitiiti e uiga i le faatulagaga o le Raspberry lava ia.

O loʻo ou faia faʻataʻitaʻiga i luga ole Raspberry PI OS (32 bit) faʻavae ile Debian Buster, Version: Aokuso 2020,
Aso faʻamalolo: 2020-08-20, Kernel version:5.4.

E lua mea e tatau ona e faia:

fa'asa'o le faila config.txt;
fatu se fa'aoga X server e galulue ai ma ni mata'itū e lua.

A fa'asa'o le faila /boot/config.txt e te mana'omia:

faʻagata le faʻaogaina o le i2c, i2s, spi;
fa'ataga le fa'aoga DPI e fa'aaoga ai le overlay dtoverlay=dpi24;
fetuutuunai ala vitio 1280 × 720 60Hz, 24 bits i pika ile DPI;
faʻamaonia le numera manaʻomia o framebuffers 2 (max_framebuffers = 2, ona faʻaalia lea o le masini lona lua / dev / fb1)

O le tusitusiga atoa o le faila config.txt e pei o lenei.

# For more options and information see
# http://rpf.io/configtxt
# Some settings may impact device functionality. See link above for details

# uncomment if you get no picture on HDMI for a default "safe" mode
#hdmi_safe=1

# uncomment this if your display has a black border of unused pixels visible
# and your display can output without overscan
disable_overscan=1

# uncomment the following to adjust overscan. Use positive numbers if console
# goes off screen, and negative if there is too much border
#overscan_left=16
#overscan_right=16
#overscan_top=16
#overscan_bottom=16

# uncomment to force a console size. By default it will be display's size minus
# overscan.
#framebuffer_width=1280
#framebuffer_height=720

# uncomment if hdmi display is not detected and composite is being output
hdmi_force_hotplug=1

# uncomment to force a specific HDMI mode (this will force VGA)
#hdmi_group=1
#hdmi_mode=1

# uncomment to force a HDMI mode rather than DVI. This can make audio work in
# DMT (computer monitor) modes
#hdmi_drive=2

# uncomment to increase signal to HDMI, if you have interference, blanking, or
# no display
#config_hdmi_boost=4

# uncomment for composite PAL
#sdtv_mode=2

#uncomment to overclock the arm. 700 MHz is the default.
#arm_freq=800

# Uncomment some or all of these to enable the optional hardware interfaces
#dtparam=i2c_arm=on
#dtparam=i2s=on
#dtparam=spi=on

dtparam=i2c_arm=off
dtparam=spi=off
dtparam=i2s=off

dtoverlay=dpi24
overscan_left=0
overscan_right=0
overscan_top=0
overscan_bottom=0
framebuffer_width=1280
framebuffer_height=720
display_default_lcd=0
enable_dpi_lcd=1
dpi_group=2
dpi_mode=87
#dpi_group=1
#dpi_mode=4
dpi_output_format=0x6f027
dpi_timings=1280 1 110 40 220 720 1 5 5 20 0 0 0 60 0 74000000 3

# Uncomment this to enable infrared communication.
#dtoverlay=gpio-ir,gpio_pin=17
#dtoverlay=gpio-ir-tx,gpio_pin=18

# Additional overlays and parameters are documented /boot/overlays/README

# Enable audio (loads snd_bcm2835)
dtparam=audio=on

[pi4]
# Enable DRM VC4 V3D driver on top of the dispmanx display stack
#dtoverlay=vc4-fkms-v3d
max_framebuffers=2

[all]
#dtoverlay=vc4-fkms-v3d
max_framebuffers=2

A maeʻa lenei mea, e tatau ona e fatuina se faila faʻapipiʻi mo le X server e faʻaoga ai ni siaki se lua i luga o le lua framebuffers / dev / fb0 ma / dev / fb1:

O laʻu faila faila /usr/share/x11/xorg.conf.d/60-dualscreen.conf e pei o lenei

Section "Device"
        Identifier      "LCD"
        Driver          "fbturbo"
        Option          "fbdev" "/dev/fb0"
        Option          "ShadowFB" "off"
        Option          "SwapbuffersWait" "true"
EndSection

Section "Device"
        Identifier      "HDMI"
        Driver          "fbturbo"
        Option          "fbdev" "/dev/fb1"
        Option          "ShadowFB" "off"
        Option          "SwapbuffersWait" "true"
EndSection

Section "Monitor"
        Identifier      "LCD-monitor"
        Option          "Primary" "true"
EndSection

Section "Monitor"
        Identifier      "HDMI-monitor"
        Option          "RightOf" "LCD-monitor"
EndSection

Section "Screen"
        Identifier      "screen0"
        Device          "LCD"
        Monitor         "LCD-monitor"
EndSection

Section "Screen"
        Identifier      "screen1"
        Device          "HDMI" 
	Monitor         "HDMI-monitor"
EndSection

Section "ServerLayout"
        Identifier      "default"
        Option          "Xinerama" "on"
        Option          "Clone" "off"
        Screen 0        "screen0"
        Screen 1        "screen1" RightOf "screen0"
EndSection

Ia, afai e leʻi faʻapipiʻiina, ona e manaʻomia lea ona faʻapipiʻi Xinerama. Ona faʻalauteleina atoa lea o le avanoa o le desktop i ni siaki se lua, e pei ona faʻaalia i le ata vitio o loʻo i luga.

Masalo ona pau lava lena. I le taimi nei, o le a mafai e le au Raspberry Pi3 ona faʻaogaina ni siaki se lua.

E mafai ona maua le fa'amatalaga ma le fa'asologa o le laupapa Mars Rover2rpi vaai iinei.

puna: www.habr.com

Mataitu lona lua HDMI i le Raspberry Pi3 e ala i le DPI interface ma le laupapa FPGA