Sezvatinoziva, shanduko kune 3 nm process tekinoroji ichaperekedzwa neshanduko kune itsva transistor architecture. Mune Samsung mazwi, semuenzaniso, aya achave MBCFET (Multi Bridge Channel FET) transistors, umo iyo transistor chiteshi ichaita senge nzira dzinoverengeka dziri pamusoro peimwe nenzira yenanopages, yakakomberedzwa nemativi ese gedhi (kuti uwane rumwe ruzivo. , maona ).
Sekureva kwevagadziri kubva kuBelgian centre Imec, iyi inofambira mberi, asi isiri yakanaka, transistor chimiro uchishandisa akachinjika FinFET magedhi. Yakanakira tekinoroji maitiro ane zvikero zvisingasviki 3 nm , iyo yakakurudzirwa nevaBelgians.
Imec yakagadzira transistor ine kupatsanurwa mapeji kana Forksheet. Aya ndiwo akafanana vertical nanopages se transistor chiteshi, asi akaparadzaniswa neinomira dielectric. Kune rumwe rutivi rwe dielectric, transistor ine n-channel inogadzirwa, kune imwe, ine p-channel. Uye ose ari maviri akakomberedzwa neakajairika shutter muchimiro chembabvu yakatwasuka.
Kuderedza iyo pa-chip chinhambwe pakati pema transistors ane akasiyana maconductivity nderimwe dambudziko hombe rekuwedzera kudzika. TCAD simulations yakasimbisa kuti kupatsanurwa-peji transistor yaizopa kuderedzwa kwe20 muzana munzvimbo yekufa. Kazhinji, iyo nyowani transistor architecture ichadzikisa yakajairwa logic cell kureba kusvika 4,3 tracks. Iyo sero ichava nyore, iyo inoshandawo pakugadzirwa kweSRAM memory cell.
Kuchinja kuri nyore kubva kune nanopage transistor kuenda kune kupatsanurwa nanopage transistor ichapa 10% kuwedzera kwekuita paunenge uchichengetedza kushandiswa, kana 24% kuderedza kushandiswa pasina kuwedzera kushanda. Simulations ye2nm process yakaratidza kuti sero reSRAM rinoshandisa nanopages rakapatsanurwa raizopa kuderedzwa kwenzvimbo yakabatanidzwa uye kuvandudzwa kwekuita kweanosvika makumi matatu muzana nep- uye n-junction spacing inosvika 30 nm.
Source: 3dnews.ru