Purojekiti yeVortex 3.0, iyo inogadzira GPGPU yakavhurika yakavakirwa pahurongwa hwemirairo yeRISC-V uye yakagadzirirwa komputa yakafanana ichishandisa OpenCL API uye SIMT (Single Instruction, Multiple Threads) execution model, yava kuwanikwa. Purojekiti iyi inogona zvakare kushandiswa pakutsvagisa mifananidzo ye3D uye kugadzira magadzirirwo matsva eGPU. Magadzirirwo, tsananguro dzemabhuroko ehardware muVerilog, simulator, madhiraivha, uye magwaro ekugadzira anoperekedza zvinogoverwa pasi perezenisi reApache 2.0.
GPGPU yakavakirwa paRISC-V ISA yakajairwa, yakawedzerwa nemimwe mirairo yekutsigira maficha eGPU uye manejimendi yethread. Kuchinja kune RISC-V instruction set architecture kunochengetwa kuri kushoma, uye mirairo yevector iripo inoshandiswa pese pazvinogoneka. Mimwe mirairo inosanganisira: "tex" yekukurumidzisa texture processing; vx_rast yekudzora rasterization; vx_rop yekugadzirisa fragment, depth, uye transparency; vx_imadd ye multiple-and-add operations; vx_wspawn, vx_split, vx_join, vx_tmc, uye vx_bar yekukurudzira mapoka ethreads (wavefronts) anoitwa pamwe chete neSIMD Engine.
GPGPU iri kugadzirwa inotsigira 32- uye 64-bit RISC-V RV32IMF uye RV64IMAFD instruction set architectures uye inogona kusanganisira optional shared memory, L1, L2, uye L3 caches, uye configurable number yemacores, warp, uye threads. Core yega yega inogonawo kusanganisira configurable number yemaALU, FPUs, LSUs, uye SFUs. Xilinx neAltera FPGAs dzinogona kushandiswa pakugadzira ma prototyping, uye Verilator (Verilog simulator), RTLSIM (RTL simulation), uye SimX (software simulation) dzinogona kushandiswa pakuita chip simulation.
Pakugadzira maapplication, pane toolkit inopihwa, kusanganisira Vortex-adapted versions dzePoCL (OpenCL compiler and runtime), LLVM/Clang, GCC, uye Binutils. Chirongwa ichi chinotsigira OpenCL 1.2 specification uye chinopa rutsigiro rweSPIR-V intermediate representation yemashaders kuburikidza nekushandura kuenda kuOpenCL.
Shanduko muVortex 3.0 dzinosanganisira:
- Mutsetse wemifananidzo yehardware wawedzerwa, kusanganisira mabhuroko ekuisa rasterization, texture mapping, uye output merging (OM). Mutyairi weVulkan, vortexpipe, wakagadzirwa weMesa zvichibva pane mutsetse wemifananidzo wakagadzirwa uye rasterizer yesoftware yelavapipe.
- Kugona kweTensor Core, yakagadzirirwa kukurumidzisa kuitwa kwemamodheru ekudzidza kwemuchina, kwakawedzerwa, zvichibatsira kutsigira sparsity yakarongwa yekudzvanya huremu hwemamita.
- Kushanda kweWGMMA (warpgroup-level matrix multiplication) kwakaitwa kuti matrix multiplication iite asynchronous mode.
- Yakawedzera injini yeDXA (Data Transfer Acceleration) kuti ikurumidze kutamisa data kubva ku global kuenda ku local memory.
- Magadzirirwo matsva akagadzirwa zvichibva pakushandisa command processor (CP) uye hardware scheduler ye computing cores (KMU - Kernel Management Unit), iyo inobvumira kutumira ma threads e computing kudivi re chip.
- Raibhurari itsva yeruntime yarongwa inoshanda nenzira isingavharidzi uye inopa ma abstractions anoshandura kuita mirairo yehardware yakaitwa nenzira isingachinji. Mitsetse, zviitiko, ma modules, uye kuenderana kwakavakirwa pazvipingamupinyi zvisingachinji ne arrive/wait/event semantics zvinotsigirwa.
- Rutsigiro rwakawedzerwa rweRISC-V Shortened Instructions (RVC).
- Rutsigiro rwemidziyo yemagetsi yekushanda kweatomu (Hardware Atomics) rwaitwa.
- FPU yakagadziriswazve zvizere uye mabhuroko matsva ekuwedzera (Wallace-tree, Folded-radix) uye adder (Kogge-Stone) akaiswa.
- Yakawedzera virtual memory stack yakavakirwa pa memory management unit (MMU) nerutsigiro rwe32-bit SV32 virtual addressing architecture.
- Rutsigiro rwekuwedzera kweRISC-V Zicond nekushandisa mashandiro ane conditional operations.
- Kuvharwa kwewachi kwakabatana.
- Rutsigiro rwemutauro weHIP (Heterogeneous Interface for Portability) rwakaitwa kuburikidza ne chipStar framework, iyo inoshandura HIP kuita SPIR-V.
- Kubatanidzwa kwakazara neGEM5 simulator kwapihwa, uye rutsigiro rweSimX simulator paTLM (Transaction-Level Modeling) architecture rwawedzerwa.
- Rutsigiro rwakawedzerwa rweSynopsys neYosys toolkits dzekugadzirisa logic yekugadzira machipisi, pamwe nerutsigiro rwekushandisa maraibhurari eASAP7 (7nm), SAED14 (14nm), uye NanGate (15nm) akajairika.
- Chishandiso chekushandisa chereferensi chakagadziridzwa kuita LLVM 20 nePOCL 7.0.
Source: opennet.ru
