{"id":56073,"date":"2020-02-04T00:00:00","date_gmt":"2020-02-03T21:00:00","guid":{"rendered":"https:\/\/prohoster.info\/blog\/blog_prohoster\/neizbezhnost-proniknoveniya-fpga-v-data-tsentry"},"modified":"2020-02-18T14:04:16","modified_gmt":"2020-02-18T11:04:16","slug":"neizbezhnost-proniknoveniya-fpga-v-data-tsentry","status":"publish","type":"post","link":"https:\/\/prohoster.info\/sq\/blog\/administrirovanie\/neizbezhnost-proniknoveniya-fpga-v-data-tsentry","title":{"rendered":"Pashmangshm\u00ebria e infiltrimit t\u00eb FPGA n\u00eb qendrat e t\u00eb dh\u00ebnave","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

\"Pashmangshm\u00ebria
\nNuk\u00eb \u00ebsht\u00eb e nevojshme t\u00eb jesh nj\u00eb zhvillues \u00e7ipesh p\u00ebr t\u00eb programuar p\u00ebr FPGA, ashtu si\u00e7 nuk \u00ebsht\u00eb e nevojshme t\u00eb jesh nj\u00eb programues n\u00eb C++ p\u00ebr t\u00eb shkruar kod n\u00eb Java. Sidoqoft\u00eb, n\u00eb t\u00eb dy rastet, \u00ebsht\u00eb e mundur q\u00eb kjo t\u00eb mos jet\u00eb e tep\u00ebrt.<\/p>\n

Q\u00ebllimi i komercializimit t\u00eb t\u00eb dy teknologjive, Java dhe FPGA, \u00ebsht\u00eb t\u00eb hedhin posht\u00eb k\u00ebt\u00eb deklarat\u00eb t\u00eb fundit. Lajmi i mir\u00eb p\u00ebr FPGA \u00ebsht\u00eb se, duke p\u00ebrdorur nivelet e duhura t\u00eb abstraksionit dhe mjetet, n\u00eb 35 vitet e fundit, q\u00eb nga shpikja e pajisjeve logjike t\u00eb programueshme, \u00ebsht\u00eb b\u00ebr\u00eb gjithnj\u00eb e m\u00eb e leht\u00eb t\u00eb krijosh algoritme dhe rrjedha t\u00eb dh\u00ebnash p\u00ebr FPGA n\u00eb vend t\u00eb CPU-ve, DSP-ve, GPU-ve ose ndonj\u00eb forme tjet\u00ebr ASIC t\u00eb specializuar.<\/p>\n

Mrekullia e krijimit t\u00eb tyre p\u00ebrputhet me faktin se pik\u00ebrisht kur CPU-t\u00eb nuk mund t\u00eb vazhdojn\u00eb t\u00eb jen\u00eb moduli i vet\u00ebm p\u00ebr llogaritje. qendrat e t\u00eb dh\u00ebnave<\/a> p\u00ebr t\u00eb p\u00ebrfunduar shum\u00eb detyra \u2013 p\u00ebr arsye t\u00eb ndryshme \u2013 FPGA arrit\u00ebn efektivitetin e tyre, duke ofruar performanc\u00eb, vones\u00eb t\u00eb ul\u00ebt, mund\u00ebsi rrjetesh dhe memorie \u2013 kapacitetet e larmishme t\u00eb llogaritjeve moderne t\u00eb FPGA SoC, q\u00eb p\u00ebrb\u00ebjn\u00eb praktikisht sisteme t\u00eb plota llogarit\u00ebse. Megjithat\u00eb, FPGA p\u00ebrputhen mir\u00eb edhe me pajisje t\u00eb tjera n\u00eb sisteme hibride, dhe, sipas mendimit ton\u00eb, ato sapo kan\u00eb filluar t\u00eb gjejn\u00eb vendin e tyre legjitim n\u00eb hierarkin\u00eb e llogaritjeve.
\n<\/a><\/noindex>
\nPrandaj ne organizuam konferenc\u00ebn The Next FPGA Platform n\u00eb San Jose m\u00eb 22 Janar. Natyrisht, nj\u00eb nga furnizuesit kryesor\u00eb t\u00eb FPGA n\u00eb bot\u00eb dhe pionier n\u00eb k\u00ebt\u00eb fush\u00eb \u00ebsht\u00eb kompania Xilinx. Ivo Bolesens, z\u00ebvend\u00ebs presidenti i lart\u00eb dhe drejtori teknik i Xilinx, foli n\u00eb konferenc\u00eb dhe na tregoi mendimet e tij t\u00eb sotme lidhur me m\u00ebnyr\u00ebn se si Xilinx ndihmon n\u00eb krijimin e sistemeve llogarituese t\u00eb modifikueshme p\u00ebr qendrat e t\u00eb dh\u00ebnave.<\/p>\n

Arkitekt\u00ebt sistemik\u00eb dhe programuesit kan\u00eb kaluar mjaft koh\u00eb p\u00ebr t\u00eb arritur n\u00eb nj\u00eb qend\u00ebr t\u00eb dh\u00ebnash t\u00eb ndryshme, ku do t\u00eb p\u00ebrfaq\u00ebsohen kapacitetet kompjuterike t\u00eb llojeve t\u00eb ndryshme, q\u00eb zgjidhin detyra rreth llogaritjes, ruajtjes dhe organizimit t\u00eb rrjeteve. Kjo duket e nevojshme p\u00ebr shkak se ndjekja e ligjit t\u00eb Murit, duke p\u00ebrdorur KMOPl t\u00eb ndryshme, po b\u00ebhet gjithnj\u00eb e m\u00eb e v\u00ebshtir\u00eb. Nd\u00ebrkoh\u00eb, gjuha jon\u00eb akoma \u00ebsht\u00eb e lidhur me CPU-n\u00eb, dhe ne akoma flasim p\u00ebr \"shpejtimin e aplikacioneve\", duke kuptuar p\u00ebrmir\u00ebsimin e performanc\u00ebs s\u00eb programeve krahasuar me at\u00eb q\u00eb mund t\u00eb b\u00ebhet vet\u00ebm me CPU-t\u00eb. Pas pak koh\u00ebsh, qendrat e t\u00eb dh\u00ebnave do t\u00eb shnd\u00ebrrohen n\u00eb grumbuj kapacitetesh llogarit\u00ebse, ruajtjesh t\u00eb dh\u00ebnash dhe protokollesh q\u00eb lidhin gjith\u00e7ka s\u00eb bashku, dhe ne do t\u00eb kthehemi n\u00eb terma si \"llogaritje\" dhe \"aplikacione\". Llogaritjet hibride do t\u00eb b\u00ebhen nj\u00eb norm\u00eb e nj\u00ebjt\u00eb me sh\u00ebrbimet \"n\u00eb re\" t\u00eb sotme, t\u00eb cilat funksionojn\u00eb mbi baz\u00ebn e zakonshme ose makinat virtuale<\/a>, dhe n\u00eb nj\u00eb \u00e7ast do t\u00eb p\u00ebrdorim thjesht fjal\u00ebn \"llogaritje\" p\u00ebr t\u00eb p\u00ebrshkruar funksionimin e tyre. N\u00eb nj\u00eb \u00e7ast \u2013 dhe ndoshta ardhja e k\u00ebsaj ere do t\u00eb nxis\u00eb aktivisht FPGA-t\u00eb \u2013 ne do ta quajm\u00eb p\u00ebrs\u00ebri k\u00ebt\u00eb p\u00ebrpunim t\u00eb dh\u00ebnash.<\/p>\n

P\u00ebr t\u00eb integruar FPGA-t\u00eb n\u00eb qendrat e t\u00eb dh\u00ebnave, do t\u00eb nevojitet t\u00eb ndryshohet m\u00ebnyra e t\u00eb menduarit. \"Duke reflektuar mbi m\u00ebnyrat p\u00ebr t\u00eb acceleruar aplikacionet e sotme, \u00ebsht\u00eb e nevojshme t\u00eb zbulojm\u00eb thelbin e asaj se si ato zbatohen, cilat burime p\u00ebrdoren, p\u00ebr \u00e7far\u00eb koh\u00eb shpenzohet,\" shpjegon Bolens. \"Duhet t\u00eb shqyrtojm\u00eb problemin e p\u00ebrgjithsh\u00ebm q\u00eb po p\u00ebrpiqeni t\u00eb zgjidhni. Shum\u00eb aplikacione, q\u00eb funksionojn\u00eb n\u00eb qendrat e t\u00eb dh\u00ebnave sot, jan\u00eb t\u00eb shkall\u00ebzueshme, duke kapur nj\u00eb num\u00ebr t\u00eb madh burimesh. Merrni p\u00ebr shembull, m\u00ebsimin e makinave, q\u00eb p\u00ebrdor nj\u00eb sasi t\u00eb madhe 'nyjesh llogarit\u00ebse'. Por duke folur p\u00ebr akcelerimin, duhet t\u00eb mendojm\u00eb jo vet\u00ebm p\u00ebr akcelerimin e llogaritjeve, por edhe p\u00ebr akcelerimin e infrastruktur\u00ebs.\"<\/p>\n

P\u00ebr shembuj, n\u00eb ato operacione q\u00eb kan\u00eb t\u00eb b\u00ebjn\u00eb me m\u00ebsimin e makinave q\u00eb Bolens ka studiuar n\u00eb praktik\u00eb, rreth 50% e koh\u00ebs shpenzohet n\u00eb transferimin e t\u00eb dh\u00ebnave nga nj\u00ebra an\u00eb n\u00eb tjetr\u00ebn mes kapaciteteve t\u00eb shp\u00ebrndara llogaritative, dhe vet\u00ebm gjysma e mbetur e koh\u00ebs shpenzohet n\u00eb vet\u00eb llogaritjet.<\/p>\n

K\u00ebtu, mendoj se FPGA mund t\u00eb ndihmoj\u00eb, sepse mund t\u00eb sigurojm\u00eb optimizimin e aspekteve t\u00eb llogaritjes dhe t\u00eb aspekteve t\u00eb transmetimit t\u00eb t\u00eb dh\u00ebnave p\u00ebr aplikacionin. Dhe ne mund ta b\u00ebjm\u00eb k\u00ebt\u00eb n\u00eb nivelin e infrastruktur\u00ebs s\u00eb p\u00ebrgjithshme dhe n\u00eb nivelin e \u00e7ipit. Kjo \u00ebsht\u00eb nj\u00eb nga avantazhet e m\u00ebdha t\u00eb FPGA, q\u00eb lejojn\u00eb krijimin e rrjeteve t\u00eb komunikimit p\u00ebr nevojat specifike t\u00eb aplikacionit. Duke v\u00ebzhguar modelet tipike t\u00eb l\u00ebvizjes s\u00eb t\u00eb dh\u00ebnave n\u00eb detyrat q\u00eb kan\u00eb t\u00eb b\u00ebjn\u00eb me inteligjenc\u00ebn artificiale, nuk shoh nevoj\u00ebn p\u00ebr nj\u00eb arkitektur\u00eb t\u00eb nd\u00ebrlikuar t\u00eb bazuar n\u00eb \u00e7switch. Mund t\u00eb nd\u00ebrtojm\u00eb nj\u00eb rrjet me nj\u00eb fluks t\u00eb lart\u00eb t\u00eb t\u00eb dh\u00ebnave. E nj\u00ebjta gj\u00eb vlen edhe p\u00ebr detyrat e trajnimit t\u00eb rrjeteve nervore \u2013 mund t\u00eb nd\u00ebrtojm\u00eb nj\u00eb rrjet celular me madh\u00ebsi paketash q\u00eb p\u00ebrshtaten me detyr\u00ebn specifike. Me p\u00ebrdorimin e FPGA-s, mund t\u00eb p\u00ebrmasojm\u00eb dhe p\u00ebrshtatnim shum\u00eb me sakt\u00ebsi protokollet e transmetimit t\u00eb t\u00eb dh\u00ebnave dhe topologjin\u00eb e skem\u00ebs p\u00ebr aplikacionin specifik. Po ashtu, n\u00eb rastin e m\u00ebsimit t\u00eb makinave, \u00ebsht\u00eb e qart\u00eb se nuk na duhen numra me pik\u00eb fluturuese me sakt\u00ebsi t\u00eb dyfisht\u00eb, dhe k\u00ebt\u00eb mund ta p\u00ebrshtatim gjithashtu.<\/p>\n

Dallimi midis FPGA dhe CPU ose ASIC-ve t\u00eb especializuara \u00ebsht\u00eb se t\u00eb fundit programohen n\u00eb prodhim dhe pas k\u00ebsaj nuk mund t\u00eb ndryshoni mendjen sa i p\u00ebrket llojeve t\u00eb t\u00eb dh\u00ebnave t\u00eb llogaritura ose elementeve t\u00eb llogaritura, ose natyr\u00ebs s\u00eb fluksit t\u00eb t\u00eb dh\u00ebnave q\u00eb kalojn\u00eb p\u00ebrmes pajisjes. FPGA-t\u00eb ju lejojn\u00eb t\u00eb ndryshoni mendimin, n\u00ebse kushtet e pun\u00ebs ndryshojn\u00eb.<\/p>\n

N\u00eb t\u00eb kaluar\u00ebn, ky avantazh kishte nj\u00eb kosto t\u00eb lart\u00eb, kur programimi p\u00ebr FPGA ishte i destinuar p\u00ebr ata q\u00eb nuk e kishin shpirtin e fort\u00eb. Duhet t\u00eb hapni kompajler\u00ebt p\u00ebr FPGA, n\u00eb m\u00ebnyr\u00eb q\u00eb ata t\u00eb integrtohen m\u00eb mir\u00eb me mjetet q\u00eb p\u00ebrdoren nga programuesit p\u00ebr t\u00eb krijuar aplikacione me llogaritje paralele p\u00ebr CPU n\u00eb gjuh\u00ebt C, C++ ose Python, dhe t\u00eb dor\u00ebzoni nj\u00eb pjes\u00eb t\u00eb pun\u00ebs n\u00eb bibliotekat q\u00eb shpejtojn\u00eb procedurat n\u00eb FPGA. K\u00ebshtu, merret me k\u00ebt\u00eb, steku p\u00ebr m\u00ebsimin e makinave Vitis, i cili \u00ebsht\u00eb n\u00eb themel t\u00eb platformave t\u00eb tilla p\u00ebr AI si Caffe dhe TensorFlow, dhe ka biblioteka p\u00ebr ekzekutimin e modeleve t\u00eb zakonshme t\u00eb AI-s\u00eb ose p\u00ebr t\u00eb shtuar aft\u00ebsit\u00eb e FPGA p\u00ebr detyra t\u00eb tilla si rikodimi i videove, njohja e objekteve n\u00eb video, analiza e t\u00eb dh\u00ebnave, menaxhimi i rrezikut financiar dhe \u00e7do bibliotek\u00eb t\u00eb jashtme.<\/p>\n

Ky kjo koncept nuk ndryshon shum\u00eb nga projekti CUDA i Nvidia, i lan\u00e7uar dhjet\u00eb vjet m\u00eb par\u00eb, i cili transferon llogarit\u00eb paralele n\u00eb GPU-akselerator\u00eb, apo nga paketa e mjeteve ROCm t\u00eb AMD-s\u00eb, apo nga premtimet e projektit Intel, OneAPI, i cili duhet t\u00eb funksionoj\u00eb n\u00eb CPU, GPU dhe FPGA t\u00eb ndryshme.<\/p>\n

\u00c7\u00ebshtja \u00ebsht\u00eb se si do t\u00eb lidhen s\u00eb bashku t\u00eb gjitha k\u00ebto mjete, n\u00eb m\u00ebnyr\u00eb q\u00eb \u00e7do k\u00ebndv\u00ebshtrim t\u00eb mund t\u00eb programoj\u00eb nj\u00eb s\u00ebr\u00eb kapacitetesh llogarit\u00ebse sipas d\u00ebshires s\u00eb tij. Kjo \u00ebsht\u00eb e r\u00ebnd\u00ebsishme sepse FPGA-t\u00eb jan\u00eb b\u00ebr\u00eb m\u00eb t\u00eb komplikuara, shum\u00eb m\u00eb t\u00eb komplikuara se \u00e7do CPU aktuale. Ato prodhohen me proceset teknologjike m\u00eb t\u00eb avancuara dhe me teknologjit\u00eb m\u00eb moderne t\u00eb paketimit t\u00eb \u00e7ipave. Dhe ato do t\u00eb gjejn\u00eb nj\u00eb ni\u015f\u00eb, pasi ne nuk mund t\u00eb humbasim m\u00eb koh\u00eb, para, energji dhe inteligjenc\u00eb \u2013 t\u00eb gjitha k\u00ebto jan\u00eb burime shum\u00eb t\u00eb shtrenjta.<\/p>\n

\u00abFPGA-t\u00eb ofrojn\u00eb avantazhe teknologjike,\u00bb thot\u00eb Bolzens. \u00abDhe kjo nuk \u00ebsht\u00eb thjesht nj\u00eb reklam\u00eb rreth adaptueshm\u00ebris\u00eb dhe ri-njoftueshm\u00ebris\u00eb. N\u00eb t\u00eb gjitha aplikacionet e r\u00ebnd\u00ebsishme \u2013 m\u00ebsimi nga makinat, analiza e grafik\u00ebve, tregtia me shpejt\u00ebsi t\u00eb lart\u00eb, etj. \u2013 ato kan\u00eb mund\u00ebsin\u00eb t\u00eb adaptojn\u00eb jo vet\u00ebm rrug\u00ebn e p\u00ebrhapjes s\u00eb t\u00eb dh\u00ebnave p\u00ebr nj\u00eb detyr\u00eb specifike, por edhe arkitektur\u00ebn e memories \u2013 m\u00ebnyr\u00ebn se si t\u00eb dh\u00ebnat l\u00ebvizin brenda \u00e7ipit. Po ashtu, n\u00eb FPGA ka shum\u00eb m\u00eb tep\u00ebr memory sesa n\u00eb pajisje t\u00eb tjera. Gjithashtu, duhet t\u00eb merret parasysh se n\u00ebse detyra nuk n\u00ebnt\u00ebrohet n\u00eb nj\u00eb FPGA, ajo mund t\u00eb shkall\u00ebzohet n\u00eb disa \u00e7ipa, pa u p\u00ebrballur me ato disavantazhe q\u00eb ju presin kur shkall\u00ebzoni detyrat n\u00eb disa CPU ose GPU\u00bb.
\n
Burimi: habr.com<\/a><\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"

\u041d\u0435 \u043d\u0443\u0436\u043d\u043e \u0431\u044b\u0442\u044c \u0440\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u0447\u0438\u043a\u043e\u043c \u0447\u0438\u043f\u043e\u0432, \u0447\u0442\u043e\u0431\u044b \u043f\u0440\u043e\u0433\u0440\u0430\u043c\u043c\u0438\u0440\u043e\u0432\u0430\u0442\u044c \u0434\u043b\u044f FPGA, \u043a\u0430\u043a \u043d\u0435 \u043d\u0443\u0436\u043d\u043e \u0431\u044b\u0442\u044c \u043f\u0440\u043e\u0433\u0440\u0430\u043c\u043c\u0438\u0441\u0442\u043e\u043c \u043d\u0430 \u0421++, \u0447\u0442\u043e\u0431\u044b \u043f\u0438\u0441\u0430\u0442\u044c \u043a\u043e\u0434 \u043d\u0430 Java. \u041e\u0434\u043d\u0430\u043a\u043e \u0432 \u043e\u0431\u043e\u0438\u0445 \u0441\u043b\u0443\u0447\u0430\u044f\u0445, \u0432\u0435\u0440\u043e\u044f\u0442\u043d\u043e, \u044d\u0442\u043e \u0431\u0443\u0434\u0435\u0442 \u043d\u0435 \u043b\u0438\u0448\u043d\u0438\u043c. \u0426\u0435\u043b\u044c \u043a\u043e\u043c\u043c\u0435\u0440\u0446\u0438\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u0438 \u043e\u0431\u0435\u0438\u0445 \u0442\u0435\u0445\u043d\u043e\u043b\u043e\u0433\u0438\u0439, Java \u0438 FPGA, \u0432 \u0442\u043e\u043c, \u0447\u0442\u043e\u0431\u044b \u043e\u043f\u0440\u043e\u0432\u0435\u0440\u0433\u043d\u0443\u0442\u044c \u043f\u043e\u0441\u043b\u0435\u0434\u043d\u0435\u0435 \u0437\u0430\u044f\u0432\u043b\u0435\u043d\u0438\u0435. \u0425\u043e\u0440\u043e\u0448\u0438\u0435 \u043d\u043e\u0432\u043e\u0441\u0442\u0438 \u0434\u043b\u044f FPGA \u2013 \u0441 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u043d\u0438\u0435\u043c \u043f\u043e\u0434\u0445\u043e\u0434\u044f\u0449\u0438\u0445 \u0443\u0440\u043e\u0432\u043d\u0435\u0439 \u0430\u0431\u0441\u0442\u0440\u0430\u043a\u0446\u0438\u0438 \u0438 \u043d\u0430\u0431\u043e\u0440\u0430 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