{"id":84726,"date":"2020-06-10T13:42:19","date_gmt":"2020-06-10T11:42:19","guid":{"rendered":"https:\/\/prohoster.info\/blog\/novosti-interneta\/mikroyadro-sel4-matematicheski-verificzirovano-dlya-arhitektury-risc-v"},"modified":"2020-06-10T13:42:19","modified_gmt":"2020-06-10T11:42:19","slug":"mikroyadro-sel4-matematicheski-verificzirovano-dlya-arhitektury-risc-v","status":"publish","type":"post","link":"https:\/\/prohoster.info\/sq\/blog\/novosti-interneta\/mikroyadro-sel4-matematicheski-verificzirovano-dlya-arhitektury-risc-v","title":{"rendered":"Mikro-b\u00ebrthama seL4 \u00ebsht\u00eb e verifikuar matematikisht p\u00ebr arkitektur\u00ebn RISC-V","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

Organizata RISC-V Foundation Tha<\/a><\/noindex> p\u00ebr verifikimin e funksionimit t\u00eb mikrojek\u00ebs seL4<\/a><\/noindex> n\u00eb sisteme me arkitektur\u00ebn e setit t\u00eb komandave RISC-V. Verifikimi p\u00ebrqendrohet n\u00eb provimin matematikor<\/a><\/noindex> t\u00eb besueshm\u00ebris\u00eb s\u00eb seL4, i cili tregon p\u00ebr p\u00ebrputhshm\u00ebrin\u00eb e plot\u00eb me specifikimet q\u00eb jan\u00eb p\u00ebrcaktuar n\u00eb nj\u00eb gjuh\u00eb formale. Provimi i besueshm\u00ebris\u00eb lejon p\u00ebrdorimin e<\/a><\/noindex> seL4 n\u00eb sisteme t\u00eb r\u00ebnd\u00ebsishme n\u00eb baz\u00eb t\u00eb procesor\u00ebve RISC-V RV64, q\u00eb k\u00ebrkojn\u00eb nj\u00eb nivel m\u00eb t\u00eb lart\u00eb t\u00eb besueshm\u00ebris\u00eb dhe garantojn\u00eb munges\u00ebn e defekteve. Zhvilluesit e softuerit, q\u00eb punojn\u00eb mbi mikrojek\u00ebn seL4, mund t\u00eb jen\u00eb plot\u00ebsisht t\u00eb sigurt se n\u00eb rastin e nj\u00eb defekti n\u00eb nj\u00eb pjes\u00eb t\u00eb sistemit, ky defekt nuk do t\u00eb shp\u00ebrndahet n\u00eb pjes\u00ebt e tjera t\u00eb sistemit dhe, ve\u00e7an\u00ebrisht, n\u00eb pjes\u00ebt e tij kritike. <\/p>\n

Fillimisht, mikrojek\u00eb seL4 u verifikua p\u00ebr procesor\u00ebt 32-bit ARM, dhe m\u00eb von\u00eb p\u00ebr procesor\u00ebt 64-bit x86. Vlen t\u00eb theksohet se kombinimi i arkitektur\u00ebs hap\u00ebsinore t\u00eb hardware-it RISC-V me mikrojek\u00ebn e hapur seL4 do t\u00eb mund\u00ebsoj\u00eb arritjen e nj\u00eb nivele t\u00eb re sigurie, pasi komponent\u00ebt hardware n\u00eb perspektiv\u00eb gjithashtu mund t\u00eb verifikohen plot\u00ebsisht, gj\u00eb q\u00eb nuk \u00ebsht\u00eb e mundur p\u00ebr arkitekturat hardware pron\u00ebsore. <\/p>\n

Gjat\u00eb verifikimit t\u00eb seL4 supozohet se pajisjet funksionojn\u00eb si\u00e7 \u00ebsht\u00eb deklaruar dhe specifikimi p\u00ebrshkruan plot\u00ebsisht sjelljen e sistemit, por n\u00eb realitet pajisjet nuk jan\u00eb t\u00eb lira nga gabimet, gj\u00eb q\u00eb demonstrohet mir\u00eb nga problemet q\u00eb shfaqen rregullisht n\u00eb mekanizmin e ekzekutimit spekulativ t\u00eb instruksioneve. Platformat hardware t\u00eb hapura leht\u00ebsojn\u00eb integrimin e ndryshimeve t\u00eb lidhura me sigurin\u00eb \u2014 p\u00ebr shembull, p\u00ebr t\u00eb bllokuar t\u00eb gjitha kanalet e mundshme t\u00eb rrjedhjes p\u00ebrmes kanaleve an\u00ebsore, ku \u00ebsht\u00eb shum\u00eb m\u00eb efikase t\u00eb zgjidhet problemi n\u00eb m\u00ebnyr\u00eb harduerike sesa t\u00eb k\u00ebrkohet nj\u00eb zgjidhje programore.<\/p>\n

Le t'i kujtojm\u00eb se arkitektura seL4 \u00ebsht\u00eb i njohur<\/a><\/noindex> ka nxjerr\u00eb pjes\u00ebt p\u00ebr menaxhimin e burimeve t\u00eb mikrojek\u00ebs n\u00eb hap\u00ebsir\u00ebn e p\u00ebrdoruesit dhe p\u00ebrdorimin e t\u00eb nj\u00ebjtave mjete t\u00eb ndarjes p\u00ebr burimet si p\u00ebr burimet e p\u00ebrdoruesit. Mikrojek\u00eb nuk ofron abstraktore t\u00eb gatshme t\u00eb niveleve t\u00eb larta p\u00ebr menaxhimin e skedar\u00ebve, proceseve, lidhjeve rrjet\u00ebrore etj., p\u00ebrkundrazi ajo ofron vet\u00ebm mekanizma minimale p\u00ebr menaxhimin e qasjes n\u00eb hap\u00ebsir\u00ebn fizike t\u00eb adresave, nd\u00ebrprerjet dhe burimet e procesorit. Abstraktoret e nivelit t\u00eb lart\u00eb dhe drejtuesit p\u00ebr nd\u00ebrveprimin me hardware-n realizohen ve\u00e7mas mbi mikrojek\u00eb n\u00eb form\u00ebn e detyrave q\u00eb ekzekutohen n\u00eb nivelin e p\u00ebrdoruesit. Qasja e k\u00ebtyre detyrave n\u00eb burimet q\u00eb ka mikrojek\u00eb organizohet p\u00ebrmes p\u00ebrcaktimit t\u00eb rregullave.<\/p>\n

RISC-V ofron nj\u00eb sistem t\u00eb hapur dhe fleksib\u00ebl t\u00eb instruksioneve t\u00eb makineris\u00eb, q\u00eb lejon krijimin e mikropro\u00e7esor\u00ebve p\u00ebr aplikacione t\u00eb ndryshme, pa k\u00ebrkuar t\u00eb hyra dhe pa vendosur kushte p\u00ebr p\u00ebrdorimin. RISC-V lejon krijimin e SoC t\u00eb hapura dhe procesor\u00ebve. Aktualisht, mbi baz\u00ebn e specifikimit RISC-V, kompani dhe komunitete t\u00eb ndryshme, duke p\u00ebrdorur licenca t\u00eb lira t\u00eb ndryshme (BSD, MIT, Apache 2.0) po zhvillohet<\/a><\/noindex> kan\u00eb krijuar disa dhjet\u00ebra variante t\u00eb b\u00ebrthamave t\u00eb mikropro\u00e7esor\u00ebve, SoC dhe \u00e7ip\u00ebve q\u00eb jan\u00eb tashm\u00eb n\u00eb prodhim. Mb\u00ebshtetja p\u00ebr RISC-V \u00ebsht\u00eb e pranishme q\u00eb nga versionet Glibc 2.27, binutils 2.30, gcc 7 dhe b\u00ebrthama Linux 4.15.<\/p>\n

<\/a><\/noindex><\/p>\n

Burimi: opennet.ru<\/a><\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"

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