Additional Uplinks i arkitekturen av Intel C620-systemlogic

In x86-platform architecture, two complementary trends have emerged. According to one version, the focus should be on integrating computational and control resources into a single chip. The second approach advocates for the distribution of responsibilities: the processor is equipped with a powerful bus that forms a peripheral scalable ecosystem. This forms the basis for the topology of Intel C620 system logic for high-level platforms.

The fundamental difference from the previous Intel C610 chipset lies in the expanded communication channel between the processor and the peripheral components included in the PCH chip, achieved through the use of PCIe links alongside the traditional DMI bus.

Let's take a closer look at the innovations of the Intel Lewisburg south bridge: what evolutionary and revolutionary approaches have expanded its capabilities in communication with processors?

Evolutionary changes in CPU-PCH communication

Within the evolutionary approach, the main communication channel between the CPU and the south bridge, which is the DMI (Direct Media Interface) bus, has gained support for PCIe x4 Gen3 mode with a performance of 8.0 GT/S. Previously, in the Intel C610 PCH, communication between the processor and system logic was conducted in PCIe x4 Gen 2 mode at a bandwidth of 5.0 GT/S.

Comparison of the functionality of Intel C610 and C620 system logic

Note that this subsystem is significantly more conservative than the integrated PCIe ports of the processor, which are typically used to connect GPUs and NVMe drives, where PCIe 3.0 has long been used and a transition to PCI Express Gen4 is planned.

Revolutionary changes in CPU-PCH communication

Revolutionary changes include the addition of new PCIe communication channels between the CPU and PCH, called Additional Uplinks. Physically, these are two PCI Express ports operating in PCIe x8 Gen3 and PCIe x16 Gen3 modes, both at 8.0 GT/S.

Three buses are used for communication between the CPU and Intel C620 PCH: DMI and two PCI Express ports.

What necessitated the revision of the existing communication topology with Intel C620? First, up to four 10GbE network controllers with RDMA functionality may be integrated into the PCH. Secondly, the encryption of network traffic and exchange with the storage subsystem is handled by a new and faster generation of Intel QuickAssist Technology (QAT) coprocessors, providing hardware support for compression and encryption. Lastly, the 'engine of innovation' — Innovation Engine, som endast kommer att vara tillgänglig för OEM-tillverkare.

Skalbarhet och flexibilitet

En viktig egenskap är möjligheten att välja inte bara PCH-anslutningstopologi utan också prioriteringarna för chipets interna resurser när det gäller tillgång till högkapacitets kommunikationskanaler med centralprocessorn (processorerna). Dessutom, i det speciella läget EPO (EndPoint Only Mode), ansluts PCH i status som en vanlig PCI Express-enhet som innehåller 10 GbE-resurser och Intel QAT. I detta fall är den klassiska DMI-gränssnittet samt ett antal legacy-under system som visas i svart i diagrammet inaktiverade.

Den interna arkitektur av Intel C620 PCH-chipet

Teoretiskt sett ger detta möjlighet att använda mer än en Intel C620 PCH-chip i systemet och skala funktionaliteten för 10 GbE och Intel QAT i enlighet med prestandakrav. Legacy-funktioner, som endast är nödvändiga i ett enda exemplar, kan endast aktiveras på ett av de installerade PCH-chip.

Således kommer det slutgiltiga ordet i designen att tillhöra plattformsutvecklaren, som agerar utifrån både tekniska och marknadsföringsfaktorer i enlighet med positioneringen av varje specifik produkt.

Källa: habr.com