{"id":115783,"date":"2024-05-15T02:59:19","date_gmt":"2024-05-15T00:59:20","guid":{"rendered":"https:\/\/prohoster.info\/blog\/novosti-interneta\/opublikovan-vortex-2-1-otkrytyj-gpgpu-na-baze-arhitektury-risc-v"},"modified":"2024-05-15T02:59:19","modified_gmt":"2024-05-15T00:59:20","slug":"opublikovan-vortex-2-1-otkrytyj-gpgpu-na-baze-arhitektury-risc-v","status":"publish","type":"post","link":"https:\/\/prohoster.info\/sv\/blog\/news\/opublikovan-vortex-2-1-otkrytyj-gpgpu-na-baze-arhitektury-risc-v","title":{"rendered":"Vortex 2.1 har publicerats, en \u00f6ppen GPGPU baserad p\u00e5 RISC-V-arkitekturen","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"<p>Den nya versionen av Vortex-projektet har publicerats, vilket utvecklar en \u00f6ppen GPGPU baserad p\u00e5 RISC-V arkitekturens kommandoset, vilket \u00e4r avsett f\u00f6r att utf\u00f6ra parallella ber\u00e4kningar med hj\u00e4lp av API:et OpenCL och SIMT-modellen (Single Instruction, Multiple Threads). Projektet kan ocks\u00e5 anv\u00e4ndas f\u00f6r forskning inom 3D-grafik och f\u00f6r utveckling av nya GPU-arkitekturer. Scheman, beskrivningar av h\u00e5rdvarublock p\u00e5 Verilog-spr\u00e5ket, simulatorer, drivrutiner och relaterad projektdokumentation distribueras under Apache 2.0-licensen.     <\/p>\n<p>Grunden f\u00f6r GPGPU utg\u00f6rs av den typiska ISA RISC-V, vilken har ut\u00f6kats med vissa ytterligare instruktioner som \u00e4r n\u00f6dv\u00e4ndiga f\u00f6r att st\u00f6dja GPU-funktioner och str\u00f6mhantering. \u00c4ndringar i RISC-V-instruktionsupps\u00e4ttningen har minimerats och fasta vektorinstruktionerna har utnyttjats i st\u00f6rsta m\u00f6jliga m\u00e5n. En liknande strategi anv\u00e4nds i RV64X-projektet, som ocks\u00e5 utvecklar en \u00f6ppen GPU baserad p\u00e5 RISC-V-teknologier.    <\/p>\n<p><center><img decoding=\"async\" alt=\"Vortex 2.1 har publicerats, en \u00f6ppen GPGPU baserad p\u00e5 RISC-V-arkitekturen \" src=\"\/wp-content\/uploads\/2024\/05\/9c4aeaf2db642809b7a6cf81b210833a.png\" style=\"display:block;margin: 0 auto;\" \/><\/center>        <\/p>\n<p>Vortexs huvudfunktioner:  <\/p>\n<ul>\n<li class=\"l\"> St\u00f6d f\u00f6r 32- och 64-bitars RISC-V RV32IMF och RV64IMAFD instruktionupps\u00e4ttningar.  <\/li>\n<li class=\"l\"> Konfigurerbart antal k\u00e4rnor, arbetsblock (warps) och tr\u00e5dar.  <\/li>\n<li class=\"l\"> Konfigurerbart antal ALU, FPU, LSU och SFU f\u00f6r varje k\u00e4rna.    <\/li>\n<li class=\"l\"> Konfigurerbar bredd f\u00f6r pipelineutmatning.  <\/li>\n<li class=\"l\"> Valfri delad minne och cache-minne p\u00e5 niv\u00e5erna L1, L2 och L3.    <\/li>\n<li class=\"l\"> St\u00f6d f\u00f6r OpenCL 1.2-specifikationen.  <\/li>\n<li class=\"l\"> M\u00f6jlighet till implementering p\u00e5 FPGA Altera Arria 10, Altera Stratix 10, Xilinx Alveo U50, U250, U280 och Xilinx Versal VCK5000.  <\/li>\n<li class=\"l\"> \u0420\u0430\u0441\u0448\u0438\u0440\u0435\u043d\u043d\u044b\u0435 \u0438\u043d\u0441\u0442\u0440\u0443\u043a\u0446\u0438\u0438: &#171;tex&#187; \u0434\u043b\u044f \u0443\u0441\u043a\u043e\u0440\u0435\u043d\u0438\u044f \u043e\u0431\u0440\u0430\u0431\u043e\u0442\u043a\u0438 \u0442\u0435\u043a\u0441\u0442\u0443\u0440, vx_rast \u0434\u043b\u044f \u0443\u043f\u0440\u0430\u0432\u043b\u0435\u043d\u0438\u044f \u0440\u0430\u0441\u0442\u0435\u0440\u0438\u0437\u0430\u0446\u0438\u0435\u0439, vx_rop \u0434\u043b\u044f \u043e\u0431\u0440\u0430\u0431\u043e\u0442\u043a\u0438 \u0444\u0440\u0430\u0433\u043c\u0435\u043d\u0442\u043e\u0432, \u0433\u043b\u0443\u0431\u0438\u043d\u044b \u0438 \u043f\u0440\u043e\u0437\u0440\u0430\u0447\u043d\u043e\u0441\u0442\u0438, vx_imadd \u0434\u043b\u044f \u0432\u044b\u043f\u043e\u043b\u043d\u0435\u043d\u0438\u044f \u043e\u043f\u0435\u0440\u0430\u0446\u0438\u0438 &#171;\u0443\u043c\u043d\u043e\u0436\u0438\u0442\u044c \u0438 \u0441\u043b\u043e\u0436\u0438\u0442\u044c&#187;,  vx_wspawn, vx_tmc \u0438 vx_bar  \u0434\u043b\u044f \u0430\u043a\u0442\u0438\u0432\u0430\u0446\u0438\u0438 \u0444\u0440\u043e\u043d\u0442\u043e\u0432 \u0438\u043d\u0441\u0442\u0440\u0443\u043a\u0446\u0438\u0439 \u0438 \u043f\u043e\u0442\u043e\u043a\u043e\u0432 \u0432 \u043d\u0438\u0445 (wavefront, \u043d\u0430\u0431\u043e\u0440 \u043d\u0438\u0442\u0435\u0439, \u043f\u0430\u0440\u0430\u043b\u043b\u0435\u043b\u044c\u043d\u043e \u0432\u044b\u043f\u043e\u043b\u043d\u044f\u0435\u043c\u044b\u0445 SIMD Engine), vx_split \u0438 vx_join.  <\/li>\n<li class=\"l\"> St\u00f6d f\u00f6r mellanliggande representationer av shaders SPIR-V m\u00f6jligg\u00f6rs genom \u00f6vers\u00e4ttning till OpenCL.      <\/li>\n<li class=\"l\"> F\u00f6r utveckling av applikationer erbjuds en verktygsl\u00e5da som inkluderar anpassade alternativ f\u00f6r PoCL (kompilator och OpenCL-runtime) f\u00f6r Vortex, LLVM\/Clang, GCC och Binutils.     <\/li>\n<li class=\"l\"> Simulering av chipets funktionalitet st\u00f6ds med hj\u00e4lp av Verilator (Verilog-simulator), RTLSIM (RTL-simulering) och SimX (programvarusimulering).        <\/li>\n<\/ul>\n<p>F\u00f6r grafik inom Vortex-teknologier utvecklas den \u00f6ppna GPU Skybox, som st\u00f6der Vulkan grafik-API. Prototypen Skybox, skapad p\u00e5 FPGA Altera Stratix 10 och som inkluderar 32 k\u00e4rnor (512 tr\u00e5dar), n\u00e5dde en fyllnadsprestanda p\u00e5 3.7 gigapixlar per sekund (29.4 gigatransaktioner per sekund) vid en klockfrekvens av 230 MHz. Det noteras att detta \u00e4r den f\u00f6rsta \u00f6ppna GPU:n med b\u00e5de programvaru- och h\u00e5rdvaruimplementering som st\u00f6der Vulkan.         <\/p>\n<p>Bland f\u00f6r\u00e4ndringarna i Vortex 2.1:  <\/p>\n<ul>\n<li class=\"l\"> API:et spawn_taskgroups har lagts till f\u00f6r att starta k\u00e4rnor som anv\u00e4nder lokal minne och st\u00f6djer minnesbarri\u00e4rer.\n<li class=\"l\"> Ett nytt till\u00e4gg f\u00f6r skapande av flyttbara (relocatable) bin\u00e4rk\u00e4rnor har f\u00f6reslagits.\n<li class=\"l\"> Funktioner vx_mem_reserve, vx_mem_access och vx_mem_address har lagts till i minneshanterings-API:et.\n<li class=\"l\"> Ett nytt runtime-API vx_check_occupancy har lagts till.\n<li class=\"l\"> I GPU-drivrutinen har en option lagts till f\u00f6r att kontrollera OpenCL-tester p\u00e5 lokal GPU.\n<li class=\"l\"> OpenCL-tester har lagts till som anv\u00e4nder lokal minne (psum, sgemm2, sgemm3).\n<li class=\"l\"> Speciellt anpassade versioner av biblioteken libc och librt f\u00f6r Vortex har lagts till.\n<li class=\"l\"> St\u00f6d f\u00f6r sammanslagning av n\u00e4rliggande lediga minnesblock (memory coalescing) har lagts till.\n<li class=\"l\"> Optimisering av mikroarkitekturen har genomf\u00f6rts.\n<li class=\"l\"> Ett nytt byggskript har lagts till som separerar k\u00e4llfiler fr\u00e5n byggkatalogen.      <\/ul>\n<p>K\u00e4lla: <a content=\"nofollow\" rel=\"nofollow\" href=\"https:\/\/www.opennet.ru\/opennews\/art.shtml?num=61173\">opennet.ru<\/a> <\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"<p>\u041e\u043f\u0443\u0431\u043b\u0438\u043a\u043e\u0432\u0430\u043d\u0430 \u043d\u043e\u0432\u0430\u044f \u0440\u0435\u0434\u0430\u043a\u0446\u0438\u044f \u043f\u0440\u043e\u0435\u043a\u0442\u0430 Vortex, \u0440\u0430\u0437\u0432\u0438\u0432\u0430\u044e\u0449\u0435\u0433\u043e \u043e\u0442\u043a\u0440\u044b\u0442\u044b\u0439 GPGPU \u043d\u0430 \u0431\u0430\u0437\u0435 \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440\u044b \u043d\u0430\u0431\u043e\u0440\u0430 \u043a\u043e\u043c\u0430\u043d\u0434 RISC-V, \u0440\u0430\u0441\u0441\u0447\u0438\u0442\u0430\u043d\u043d\u044b\u0439 \u043d\u0430 \u0432\u044b\u043f\u043e\u043b\u043d\u0435\u043d\u0438\u0435 \u043f\u0430\u0440\u0430\u043b\u043b\u0435\u043b\u044c\u043d\u044b\u0445 \u0432\u044b\u0447\u0438\u0441\u043b\u0435\u043d\u0438\u0439 \u0441 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u043d\u0438\u0435\u043c API OpenCL \u0438 \u043c\u043e\u0434\u0435\u043b\u0438 \u0432\u044b\u043f\u043e\u043b\u043d\u0435\u043d\u0438\u044f SIMT (Single Instruction, Multiple Threads). \u041f\u0440\u043e\u0435\u043a\u0442 \u0442\u0430\u043a\u0436\u0435 \u043c\u043e\u0436\u0435\u0442 \u0431\u044b\u0442\u044c \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u043d \u043f\u0440\u0438 \u043f\u0440\u043e\u0432\u0435\u0434\u0435\u043d\u0438\u0438 \u0438\u0441\u0441\u043b\u0435\u0434\u043e\u0432\u0430\u043d\u0438\u0439 \u0432 \u043e\u0431\u043b\u0430\u0441\u0442\u0438 3D-\u0433\u0440\u0430\u0444\u0438\u043a\u0438 \u0438 \u043f\u0440\u0438 \u0440\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u043a\u0435 \u043d\u043e\u0432\u044b\u0445 \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440 GPU. \u0421\u0445\u0435\u043c\u044b, \u043e\u043f\u0438\u0441\u0430\u043d\u0438\u044f \u0430\u043f\u043f\u0430\u0440\u0430\u0442\u043d\u044b\u0445 \u0431\u043b\u043e\u043a\u043e\u0432 \u043d\u0430 \u044f\u0437\u044b\u043a\u0435 Verilog, [&hellip;]<\/p>\n","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"author":1,"featured_media":115784,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[702],"tags":[],"class_list":["post-115783","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-news"],"aioseo_notices":[],"aioseo_head":"\n\t\t<!-- All in One SEO 5.0.4 - aioseo.com -->\n\t<meta name=\"description\" content=\"\u041e\u043f\u0443\u0431\u043b\u0438\u043a\u043e\u0432\u0430\u043d\u0430 \u043d\u043e\u0432\u0430\u044f \u0440\u0435\u0434\u0430\u043a\u0446\u0438\u044f \u043f\u0440\u043e\u0435\u043a\u0442\u0430 Vortex, \u0440\u0430\u0437\u0432\u0438\u0432\u0430\u044e\u0449\u0435\u0433\u043e \u043e\u0442\u043a\u0440\u044b\u0442\u044b\u0439 GPGPU \u043d\u0430 \u0431\u0430\u0437\u0435 \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440\u044b 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