Ushicilelo lwesibini lweprojekthi ye-Vortex ishicilelwe, iphuhlisa i-GPGPU evulekileyo esekelwe kwi-RISC-V ye-architecture ye-architecture ye-architecture, eyenzelwe ukwenza i-computing efanayo usebenzisa i-OpenCL API kunye ne-SIMT (Umyalelo omnye, i-Multiple Threads) imodeli yokuphumeza. Iprojekthi ingasetyenziselwa ukuqhuba uphando kwintsimi ye-3D yemizobo kunye nokuphuhlisa izakhiwo ezintsha ze-GPU. Izicwangciso, iinkcazo zeeyunithi ze-hardware ngolwimi lwe-Verilog, isifanisi, abaqhubi kunye namaxwebhu oyilo olukhaphayo asasazwa phantsi kwelayisensi ye-Apache 2.0.
Undoqo we-GPGPU yi-generic RISC-V ISA, eyandiswe ngeminye imiyalelo eyongezelelweyo efunekayo ukuxhasa ukusebenza kwe-GPU kunye nolawulo lwentambo. Ngexesha elifanayo, utshintsho kwi-RISC-V ye-architecture ye-architecture yomyalelo igcinwa ibe yincinci kwaye, xa kunokwenzeka, imiyalelo ekhoyo ye-vector isetyenziswa. Indlela efanayo isetyenziswa kwiprojekthi yeRV64X, ekwaphuhlisa iGPU evulekileyo esekwe kubuchwephesha beRISC-V.
Kwimizobo esekwe kwitekhnoloji yeVortex, i-GPU Skybox evulekileyo iyaphuhliswa, ixhasa i-API yemizobo yeVulkan. Iprototype ye-Skybox, eyenziwe ngesiseko se-Altera Stratix 10 FPGA kwaye ibandakanya i-32 cores (i-512 threads), yenza ukuba kube lula ukufezekisa ukusebenza kwe-230 gigapixels ngesibini (3.7 gigatransactions ngomzuzwana) kwi-frequency ye-29.4 MHz. Kuqatshelwe ukuba le yiGPU yokuqala evulekileyo enesoftware kunye nokuphunyezwa kwehardware exhasa iVulkan.
Iimpawu eziphambili zeVortex:
- Ixhasa i-32- kunye ne-64-bit ye-RISC-V yomyalelo wesethi yezakhiwo ze-RV32IMF kunye ne-RV64IMAFD.
- Inani elilungelelanisiweyo lee-cores, iibhloko zomsebenzi (i-warps) kunye nemisonto.
- Inani elilungisekayo le-ALUs, iiFPU, iiLSU kunye nee-SFUs ngondoqo ngamnye.
- Ububanzi bomba wombhobho olungisekayo.
- Imemori ekwabelwana ngayo ngokuzikhethela kunye ne-L1, L2 kunye ne-L3 cache.
- Inkxaso yenkcazo ye-OpenCL 1.2.
- Ukunokwenzeka kokuphunyezwa ngokusekelwe kwiFPGA Altera Arria 10, Altera Stratix 10, Xilinx Alveo U50, U250, U280 kunye ne-Xilinx Versal VCK5000.
- Imiyalelo engaphezulu: "i-tex" ukukhawulezisa ukucutshungulwa, i-vx_rast yokulawula i-rasterization, i-vx_rop yokuphatha amaqhekeza, ubunzulu kunye nokungafihli, i-vx_imadd ukwenza ukuphindaphinda kunye nokongeza imisebenzi, vx_wspawn, vx_tmc kunye ne-vx_bar ukuvula imiphetho yemiyalelo kunye ne-wavefronts, iseti yeentambo isetyenziswe ngokunxuseneyo yi-SIMD Engine), vx_split kunye ne-vx_join.
- Inkxaso yokumelwa okuphakathi kwee-SPIR-V shaders iphunyezwa ngokuguqulelwa kwi-OpenCL.
- Ukuphuhliswa kwesicelo, i-toolkit inikezelwa, kubandakanywa ukwahluka kwe-PoCL (umqokeleli kunye ne-runtime OpenCL), i-LLVM / Clang, i-GCC kunye ne-Binutils elungiselelwe ukusebenza ne-Vortex.
- Ukulinganisa kwe-Chip kuxhaswa kusetyenziswa i-Verilator (i-Verilog simulator), i-RTLSIM (ukulinganisa i-RTL) kunye ne-SimX (ukulinganisa isofthiwe).
Phakathi kweenguqu kwiVortex 2.0:
- I-microarchitecture iye yalungiswa.
- Inkxaso eyongeziweyo ye-64-bit ye-RISC-V RV64IMAFD yomyalelo we-architecture.
- Ukongezwa okunokwenzeka kokuphunyezwa ngokusekelwe kwi-Xilinx FPGA.
- Inkxaso eyongezelelweyo ye-LLVM 16 kunye Ubuntu 20.04.
- Uhlengahlengiso lwenziwe kwaye iziphene ezichongiweyo ngexesha lovavanyo lomgangatho zilungisiwe.
umthombo: opennet.ru
