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Atẹle HDMI keji si Rasipibẹri Pi3 nipasẹ wiwo DPI ati igbimọ FPGA


Fidio yii fihan: igbimọ Rasipibẹri Pi3, ti a ti sopọ si nipasẹ asopọ GPIO jẹ igbimọ FPGA Mars Rover2rpi (Cyclone IV), eyiti o jẹ asopọ HDMI atẹle. Atẹle keji ti sopọ nipasẹ boṣewa HDMI asopo ti Rasipibẹri Pi3. Ohun gbogbo ṣiṣẹ papọ bi eto atẹle meji.

Nigbamii Emi yoo sọ fun ọ bi eyi ṣe ṣe imuse.

Igbimọ Rasipibẹri Pi3 olokiki ni asopo GPIO nipasẹ eyiti o le sopọ ọpọlọpọ awọn kaadi imugboroosi: awọn sensosi, Awọn LED, awakọ awakọ stepper ati pupọ diẹ sii. Iṣẹ gangan ti pinni kọọkan lori asopo kan da lori iṣeto ni ibudo. Iṣeto GPIO ALT2 ngbanilaaye lati yi asopo pada si ipo wiwo DPI, Ibaraẹnisọrọ Parallel Ifihan. Awọn kaadi imugboroosi wa fun sisopọ awọn diigi VGA nipasẹ DPI. Sibẹsibẹ, ni akọkọ, awọn diigi VGA ko wọpọ bi HDMI, ati ni ẹẹkeji, wiwo oni-nọmba n pọ si dara julọ ju afọwọṣe lọ. Pẹlupẹlu, DAC lori iru awọn igbimọ imugboroja VGA nigbagbogbo ni a ṣe ni irisi awọn ẹwọn R-2-R ati nigbagbogbo ko ju awọn die-die 6 fun awọ kan.

Ni ipo ALT2, awọn pinni asopo GPIO ni itumo atẹle:

Atẹle HDMI keji si Rasipibẹri Pi3 nipasẹ wiwo DPI ati igbimọ FPGA

Nibi Mo ti ni awọ awọn pinni RGB ti asopo pupa, alawọ ewe ati buluu ni atele. Awọn ifihan agbara pataki miiran jẹ awọn ifihan agbara V-SYNC ati H-SYNC, bakanna bi CLK. Igbohunsafẹfẹ aago CLK jẹ igbohunsafẹfẹ eyiti awọn iye piksẹli ṣe jade si asopo; o da lori ipo fidio ti o yan.

Lati sopọ oni-nọmba HDMI atẹle, o nilo lati gba awọn ifihan agbara DPI ti wiwo ati yi wọn pada si awọn ifihan agbara HDMI. Eyi le ṣee ṣe, fun apẹẹrẹ, ni lilo iru igbimọ FPGA kan. Bi o ti wa ni jade, igbimọ Mars Rover2rpi dara fun awọn idi wọnyi. Ni otitọ, aṣayan akọkọ fun sisopọ igbimọ yii nipasẹ ohun ti nmu badọgba pataki kan dabi eyi:

Atẹle HDMI keji si Rasipibẹri Pi3 nipasẹ wiwo DPI ati igbimọ FPGA

A lo igbimọ yii lati mu nọmba awọn ebute oko oju omi GPIO pọ si ati lati so awọn ẹrọ agbeegbe diẹ sii si rasipibẹri. Ni akoko kanna, awọn ifihan agbara GPIO 4 pẹlu asopọ yii ni a lo fun awọn ifihan agbara JTAG, ki eto lati Rasipibẹri le gbe famuwia FPGA sinu FPGA. Nitori eyi, asopọ boṣewa ko baamu mi; Awọn ifihan agbara DPI 4 ju silẹ. Ni Oriire, awọn afikun combs lori ọkọ ni pinout ti o ni ibamu pẹlu Rasipibẹri. Nitorinaa MO le yi igbimọ naa ni iwọn 90 ati tun so pọ mọ rasipibẹri mi:

Atẹle HDMI keji si Rasipibẹri Pi3 nipasẹ wiwo DPI ati igbimọ FPGA

Nitoribẹẹ, iwọ yoo ni lati lo olutọpa JTAG ita, ṣugbọn eyi kii ṣe iṣoro.

Isoro kekere tun wa. Kii ṣe gbogbo pinni FPGA le ṣee lo bi titẹ sii aago kan. Awọn pinni igbẹhin nikan wa ti o le ṣee lo fun awọn idi wọnyi. Nitorinaa o wa nihin pe ifihan GPIO_0 CLK ko de titẹ sii FPGA, eyiti o le ṣee lo bi titẹ sii aago FPGA. Nitorinaa Mo tun ni lati fi okun waya kan sori sikafu naa. Mo so GPIO_0 ati ami ifihan KEY[1] igbimọ:

Atẹle HDMI keji si Rasipibẹri Pi3 nipasẹ wiwo DPI ati igbimọ FPGA

Bayi Emi yoo sọ fun ọ diẹ nipa iṣẹ akanṣe FPGA. Iṣoro akọkọ ni ṣiṣẹda awọn ifihan agbara HDMI jẹ awọn igbohunsafẹfẹ giga pupọ. Ti o ba wo pinout asopo ohun HDMI, o le rii pe awọn ifihan agbara RGB jẹ awọn ami iyasọtọ ni tẹlentẹle:

Atẹle HDMI keji si Rasipibẹri Pi3 nipasẹ wiwo DPI ati igbimọ FPGA

Lilo ifihan agbara iyatọ gba ọ laaye lati dojuko kikọlu ipo ti o wọpọ lori laini gbigbe. Ni idi eyi, koodu atilẹba mẹjọ-bit ti ifihan awọ kọọkan jẹ iyipada si 10-bit TMDS (Ifihan iyatọ ti o dinku-iyipada). Eyi jẹ ọna ifaminsi pataki lati yọ paati DC kuro ninu ifihan agbara ati gbe ifihan agbara yipada ni laini iyatọ. Niwọn bi awọn bit 10 ni bayi nilo lati tan kaakiri lori laini tẹlentẹle fun baiti awọ kan, o wa ni pe iyara aago serializer gbọdọ jẹ awọn akoko 10 ga ju iyara aago pixel lọ. Ti a ba mu fun apẹẹrẹ ipo fidio 1280x720 60Hz, lẹhinna igbohunsafẹfẹ pixel ti ipo yii jẹ 74,25 MHz. Serializer yẹ ki o jẹ 742,5 MHz.

Awọn FPGA deede, laanu, ko lagbara ti eyi. Sibẹsibẹ, da fun wa, FPGA ni awọn pinni DDIO ti a ṣe sinu. Iwọnyi jẹ awọn ipinnu ti o ti wa tẹlẹ, bi o ti jẹ pe, 2-to-1 serializers. Iyẹn ni, wọn le ṣe agbejade awọn die-die meji ni atẹlera lori awọn egbegbe ti nyara ati ja bo ti igbohunsafẹfẹ aago. Eyi tumọ si pe ninu iṣẹ akanṣe FPGA o le lo kii ṣe 740 MHz, ṣugbọn 370 MHz, ṣugbọn o nilo lati lo awọn eroja iṣelọpọ DDIO ninu FPGA. Bayi 370 MHz ti jẹ igbohunsafẹfẹ ti o ṣee ṣe patapata. Laanu, ipo 1280x720 jẹ opin. Ipinnu ti o ga julọ ko le ṣe aṣeyọri ninu Cyclone IV FPGA wa ti a fi sori igbimọ Mars Rover2rpi.

Nitorinaa, ninu apẹrẹ, igbohunsafẹfẹ piksẹli titẹ sii CLK lọ si PLL, nibiti o ti pọ si nipasẹ 5. Ni igbohunsafẹfẹ yii, awọn baiti R, G, B ti yipada si awọn orisii bit. Eyi ni ohun ti koodu koodu TMDS ṣe. Koodu orisun ni Verilog HDL dabi eyi:

module hdmi(
	input wire pixclk,		// 74MHz
	input wire clk_TMDS2,	// 370MHz
	input wire hsync,
	input wire vsync,
	input wire active,
	input wire [7:0]red,
	input wire [7:0]green,
	input wire [7:0]blue,
	output wire TMDS_bh,
	output wire TMDS_bl,
	output wire TMDS_gh,
	output wire TMDS_gl,
	output wire TMDS_rh,
	output wire TMDS_rl
);

wire [9:0] TMDS_red, TMDS_green, TMDS_blue;
TMDS_encoder encode_R(.clk(pixclk), .VD(red  ), .CD({vsync,hsync}), .VDE(active), .TMDS(TMDS_red));
TMDS_encoder encode_G(.clk(pixclk), .VD(green), .CD({vsync,hsync}), .VDE(active), .TMDS(TMDS_green));
TMDS_encoder encode_B(.clk(pixclk), .VD(blue ), .CD({vsync,hsync}), .VDE(active), .TMDS(TMDS_blue));

reg [2:0] TMDS_mod5=0;  // modulus 5 counter
reg [4:0] TMDS_shift_bh=0, TMDS_shift_bl=0;
reg [4:0] TMDS_shift_gh=0, TMDS_shift_gl=0;
reg [4:0] TMDS_shift_rh=0, TMDS_shift_rl=0;

wire [4:0] TMDS_blue_l  = {TMDS_blue[9],TMDS_blue[7],TMDS_blue[5],TMDS_blue[3],TMDS_blue[1]};
wire [4:0] TMDS_blue_h  = {TMDS_blue[8],TMDS_blue[6],TMDS_blue[4],TMDS_blue[2],TMDS_blue[0]};
wire [4:0] TMDS_green_l = {TMDS_green[9],TMDS_green[7],TMDS_green[5],TMDS_green[3],TMDS_green[1]};
wire [4:0] TMDS_green_h = {TMDS_green[8],TMDS_green[6],TMDS_green[4],TMDS_green[2],TMDS_green[0]};
wire [4:0] TMDS_red_l   = {TMDS_red[9],TMDS_red[7],TMDS_red[5],TMDS_red[3],TMDS_red[1]};
wire [4:0] TMDS_red_h   = {TMDS_red[8],TMDS_red[6],TMDS_red[4],TMDS_red[2],TMDS_red[0]};

always @(posedge clk_TMDS2)
begin
	TMDS_shift_bh <= TMDS_mod5[2] ? TMDS_blue_h  : TMDS_shift_bh  [4:1];
	TMDS_shift_bl <= TMDS_mod5[2] ? TMDS_blue_l  : TMDS_shift_bl  [4:1];
	TMDS_shift_gh <= TMDS_mod5[2] ? TMDS_green_h : TMDS_shift_gh  [4:1];
	TMDS_shift_gl <= TMDS_mod5[2] ? TMDS_green_l : TMDS_shift_gl  [4:1];
	TMDS_shift_rh <= TMDS_mod5[2] ? TMDS_red_h   : TMDS_shift_rh  [4:1];
	TMDS_shift_rl <= TMDS_mod5[2] ? TMDS_red_l   : TMDS_shift_rl  [4:1];
	TMDS_mod5 <= (TMDS_mod5[2]) ? 3'd0 : TMDS_mod5+3'd1;
end

assign TMDS_bh = TMDS_shift_bh[0];
assign TMDS_bl = TMDS_shift_bl[0];
assign TMDS_gh = TMDS_shift_gh[0];
assign TMDS_gl = TMDS_shift_gl[0];
assign TMDS_rh = TMDS_shift_rh[0];
assign TMDS_rl = TMDS_shift_rl[0];

endmodule

module TMDS_encoder(
	input clk,
	input [7:0] VD,	// video data (red, green or blue)
	input [1:0] CD,	// control data
	input VDE,  	// video data enable, to choose between CD (when VDE=0) and VD (when VDE=1)
	output reg [9:0] TMDS = 0
);

wire [3:0] Nb1s = VD[0] + VD[1] + VD[2] + VD[3] + VD[4] + VD[5] + VD[6] + VD[7];
wire XNOR = (Nb1s>4'd4) || (Nb1s==4'd4 && VD[0]==1'b0);
wire [8:0] q_m = {~XNOR, q_m[6:0] ^ VD[7:1] ^ {7{XNOR}}, VD[0]};

reg [3:0] balance_acc = 0;
wire [3:0] balance = q_m[0] + q_m[1] + q_m[2] + q_m[3] + q_m[4] + q_m[5] + q_m[6] + q_m[7] - 4'd4;
wire balance_sign_eq = (balance[3] == balance_acc[3]);
wire invert_q_m = (balance==0 || balance_acc==0) ? ~q_m[8] : balance_sign_eq;
wire [3:0] balance_acc_inc = balance - ({q_m[8] ^ ~balance_sign_eq} & ~(balance==0 || balance_acc==0));
wire [3:0] balance_acc_new = invert_q_m ? balance_acc-balance_acc_inc : balance_acc+balance_acc_inc;
wire [9:0] TMDS_data = {invert_q_m, q_m[8], q_m[7:0] ^ {8{invert_q_m}}};
wire [9:0] TMDS_code = CD[1] ? (CD[0] ? 10'b1010101011 : 10'b0101010100) : (CD[0] ? 10'b0010101011 : 10'b1101010100);

always @(posedge clk) TMDS <= VDE ? TMDS_data : TMDS_code;
always @(posedge clk) balance_acc <= VDE ? balance_acc_new : 4'h0;

endmodule

Lẹhinna awọn orisii abajade jẹ ifunni si iṣẹjade DDIO, eyiti o ṣe agbejade ifihan agbara kan-bit kan lori awọn egbegbe dide ati ja bo.

DDIO funrararẹ le ṣe apejuwe pẹlu koodu Verilog atẹle yii:

module ddio(
	input wire d0,
	input wire d1,
	input wire clk,
	output wire out
	);

reg r_d0;
reg r_d1;
always @(posedge clk)
begin
	r_d0 <= d0;
	r_d1 <= d1;
end
assign out = clk ? r_d0 : r_d1;
endmodule

Ṣugbọn o ṣeese kii yoo ṣiṣẹ ni ọna yẹn. O nilo lati lo Alter's megafunction ALTDDIO_OUT lati mu awọn eroja iṣelọpọ DDIO ṣiṣẹ gangan. Iṣẹ akanṣe mi nlo paati ile-ikawe ALTDDIO_OUT.

Eyi le dabi ẹtan diẹ, ṣugbọn o ṣiṣẹ.

O le wo gbogbo koodu orisun ti a kọ sinu Verilog HDL nibi lori github.

Famuwia ti o ṣajọ fun FPGA ti tan sinu chirún EPCS ti a fi sori ẹrọ lori igbimọ Mars Rover2rpi. Nitorinaa, nigbati a ba lo agbara si igbimọ FPGA, FPGA yoo wa ni ipilẹṣẹ lati iranti filasi ati bẹrẹ.

Bayi a nilo lati sọrọ kekere kan nipa iṣeto ti Rasipibẹri funrararẹ.

Mo n ṣe awọn idanwo lori Rasipibẹri PI OS (32 bit) ti o da lori Debian Buster, Ẹya: Oṣu Kẹjọ 2020,
Ọjọ idasilẹ: 2020-08-20, Ẹya Ekuro: 5.4.

O nilo lati ṣe awọn nkan meji:

  • satunkọ faili config.txt;
  • ṣẹda iṣeto olupin X kan lati ṣiṣẹ pẹlu awọn diigi meji.

Nigbati o ba n ṣatunkọ faili /boot/config.txt o nilo:

  1. mu awọn lilo ti i2c, i2s, spi;
  2. mu ipo DPI ṣiṣẹ nipa lilo agbekọja dtoverlay=dpi24;
  3. tunto ipo fidio 1280×720 60Hz, 24 die-die fun ẹbun on DPI;
  4. pato nọmba ti a beere fun awọn framebuffers 2 (max_framebuffers=2, lẹhinna nikan ni ẹrọ keji / dev/fb1 yoo han)

Ọrọ kikun ti faili config.txt dabi eyi.

# For more options and information see
# http://rpf.io/configtxt
# Some settings may impact device functionality. See link above for details

# uncomment if you get no picture on HDMI for a default "safe" mode
#hdmi_safe=1

# uncomment this if your display has a black border of unused pixels visible
# and your display can output without overscan
disable_overscan=1

# uncomment the following to adjust overscan. Use positive numbers if console
# goes off screen, and negative if there is too much border
#overscan_left=16
#overscan_right=16
#overscan_top=16
#overscan_bottom=16

# uncomment to force a console size. By default it will be display's size minus
# overscan.
#framebuffer_width=1280
#framebuffer_height=720

# uncomment if hdmi display is not detected and composite is being output
hdmi_force_hotplug=1

# uncomment to force a specific HDMI mode (this will force VGA)
#hdmi_group=1
#hdmi_mode=1

# uncomment to force a HDMI mode rather than DVI. This can make audio work in
# DMT (computer monitor) modes
#hdmi_drive=2

# uncomment to increase signal to HDMI, if you have interference, blanking, or
# no display
#config_hdmi_boost=4

# uncomment for composite PAL
#sdtv_mode=2

#uncomment to overclock the arm. 700 MHz is the default.
#arm_freq=800

# Uncomment some or all of these to enable the optional hardware interfaces
#dtparam=i2c_arm=on
#dtparam=i2s=on
#dtparam=spi=on

dtparam=i2c_arm=off
dtparam=spi=off
dtparam=i2s=off

dtoverlay=dpi24
overscan_left=0
overscan_right=0
overscan_top=0
overscan_bottom=0
framebuffer_width=1280
framebuffer_height=720
display_default_lcd=0
enable_dpi_lcd=1
dpi_group=2
dpi_mode=87
#dpi_group=1
#dpi_mode=4
dpi_output_format=0x6f027
dpi_timings=1280 1 110 40 220 720 1 5 5 20 0 0 0 60 0 74000000 3

# Uncomment this to enable infrared communication.
#dtoverlay=gpio-ir,gpio_pin=17
#dtoverlay=gpio-ir-tx,gpio_pin=18

# Additional overlays and parameters are documented /boot/overlays/README

# Enable audio (loads snd_bcm2835)
dtparam=audio=on

[pi4]
# Enable DRM VC4 V3D driver on top of the dispmanx display stack
#dtoverlay=vc4-fkms-v3d
max_framebuffers=2

[all]
#dtoverlay=vc4-fkms-v3d
max_framebuffers=2

Lẹhin eyi, o nilo lati ṣẹda faili iṣeto ni fun olupin X lati lo awọn diigi meji lori awọn fireemu meji / dev/fb0 ati / dev/fb1:

Faili iṣeto mi /usr/share/x11/xorg.conf.d/60-dualscreen.conf dabi eyi

Section "Device"
        Identifier      "LCD"
        Driver          "fbturbo"
        Option          "fbdev" "/dev/fb0"
        Option          "ShadowFB" "off"
        Option          "SwapbuffersWait" "true"
EndSection

Section "Device"
        Identifier      "HDMI"
        Driver          "fbturbo"
        Option          "fbdev" "/dev/fb1"
        Option          "ShadowFB" "off"
        Option          "SwapbuffersWait" "true"
EndSection

Section "Monitor"
        Identifier      "LCD-monitor"
        Option          "Primary" "true"
EndSection

Section "Monitor"
        Identifier      "HDMI-monitor"
        Option          "RightOf" "LCD-monitor"
EndSection

Section "Screen"
        Identifier      "screen0"
        Device          "LCD"
        Monitor         "LCD-monitor"
EndSection

Section "Screen"
        Identifier      "screen1"
        Device          "HDMI" 
	Monitor         "HDMI-monitor"
EndSection

Section "ServerLayout"
        Identifier      "default"
        Option          "Xinerama" "on"
        Option          "Clone" "off"
        Screen 0        "screen0"
        Screen 1        "screen1" RightOf "screen0"
EndSection

O dara, ti ko ba ti fi sii tẹlẹ, lẹhinna o nilo lati fi sori ẹrọ Xinerama. Lẹhinna aaye tabili tabili yoo gbooro ni kikun si awọn diigi meji, bi a ṣe han ninu fidio demo loke.

Boya iyẹn ni gbogbo rẹ. Bayi, awọn oniwun Rasipibẹri Pi3 yoo ni anfani lati lo awọn diigi meji.

Apejuwe ati aworan iyika ti igbimọ Mars Rover2rpi ni a le rii wo ibi.

orisun: www.habr.com