Iphrojekthi ye-Vortex 3.0, ethuthukisa i-GPGPU yomthombo ovulekile ngokusekelwe kusakhiwo sesethi yemiyalelo ye-RISC-V futhi yenzelwe ukubala okuhambisanayo kusetshenziswa i-OpenCL API kanye nemodeli yokusebenza ye-SIMT (Single Instruction, Multiple Threads), isiyatholakala manje. Le phrojekthi ingasetshenziswa futhi ocwaningweni lwezithombe ze-3D kanye nokuthuthukiswa kwezakhiwo ezintsha ze-GPU. Ama-schematics, izincazelo zamabhulokhi ehadiwe ku-Verilog, i-simulator, abashayeli, kanye nemibhalo yokuklama ehambisanayo isatshalaliswa ngaphansi kwelayisensi ye-Apache 2.0.
I-GPGPU isekelwe ku-RISC-V ISA ejwayelekile, enwetshiwe ngemiyalelo eyengeziwe yokusekela izici ze-GPU kanye nokuphathwa kwentambo. Izinguquko kusakhiwo sesethi yemiyalelo ye-RISC-V zigcinwa zincane kakhulu, futhi imiyalelo yevektha ekhona isetshenziswa noma nini lapho kungenzeka. Imiyalelo eyengeziwe ifaka phakathi: "tex" yokusheshisa ukucubungula ukuthungwa; i-vx_rast yokulawula i-rasterization; i-vx_rop yokucubungula izingcezu, ukujula, kanye nokucaca; i-vx_imadd yokusebenza kokuphindaphinda nokwengeza; i-vx_wspawn, i-vx_split, i-vx_join, i-vx_tmc, kanye ne-vx_bar yokuqalisa amaqembu ezintambo (ama-wavefront) aqhutshwa ngokuhambisana ne-SIMD Engine.
I-GPGPU ethuthukiswayo isekela ukwakheka kwemiyalelo ye-RISC-V RV32IMF kanye ne-RV64IMAFD engu-32- kanye ne-64-bit futhi ingafaka imemori eyabiwe ongayikhetha, ama-cache e-L1, L2, kanye ne-L3, kanye nenani elilungisekayo lama-cores, ama-warp, kanye nezintambo. I-core ngayinye ingafaka nenani elilungisekayo lama-ALU, ama-FPU, ama-LSU, nama-SFU. Ama-Xilinx kanye ne-Altera FPGA angasetshenziswa ukwenza ama-prototyping, kanti i-Verilator (i-Verilog simulator), i-RTLSIM (i-RTL simulation), kanye ne-SimX (i-software simulation) ingasetshenziswa ekulingiseni ama-chip.
Ukuze kuthuthukiswe uhlelo lokusebenza, kuhlinzekwa ithuluzi lamathuluzi, okuhlanganisa izinguqulo ze-Vortex eziguquliwe ze-PoCL (i-OpenCL compiler kanye ne-runtime), i-LLVM/Clang, i-GCC, kanye ne-Binutils. Le phrojekthi isekela imininingwane ye-OpenCL 1.2 futhi isebenzisa ukusekelwa kokumelwa okuphakathi kwe-SPIR-V kwama-shaders ngokuhumusha ku-OpenCL.
Izinguquko ku-Vortex 3.0 zifaka:
- Kufakwe i-hardware graphics stack, okuhlanganisa amabhlogo e-rasterization, i-texture mapping, kanye ne-output merging (OM). I-Vulkan driver, i-vortexpipe, yakhelwe i-Mesa ngokusekelwe ku-graphics stack esetshenzisiwe kanye ne-lavapipe software rasterizer.
- Amakhono e-Tensor Core, aklanyelwe ukusheshisa ukwenziwa kwamamodeli okufunda komshini, anwetshiwe, kusetshenziswa ukwesekwa kwe-sparsity ehlelekile yokucindezela i-weight matrices.
- Umsebenzi we-WGMMA (warpgroup-level matrix multiplication) usetshenziswe ekuphindaphindeni kwe-matrix kwimodi engahambisani.
- Kungezwe injini ye-DXA (Data Transfer Acceleration) ukuze kusheshiswe ukudluliselwa kwedatha kusuka kumemori yomhlaba wonke kuya endaweni.
- Kusetshenziswe ukwakheka okusha okusekelwe ku-command processor (CP) kanye ne-hardware scheduler yama-computing cores (KMU - Kernel Management Unit), evumela ukuthunyelwa kwezintambo zokubala ohlangothini lwe-chip.
- Kuphakanyiswa umtapo wolwazi omusha wesikhathi sokusebenza osebenza ngendlela engavimbeli futhi ohlinzeka ngezifinyezo ezihumushela emiyalweni yehadiwe eqhutshwa ngendlela engavumelani. Imigqa, imicimbi, amamojula, kanye nokuvumelanisa okusekelwe ezithiyweni ezingavumelani ezine-semantics ye-arrive/wait/event kuyasekelwa.
- Kungezwe ukwesekwa kwe-RISC-V Shortened Instructions (RVC).
- Ukusekelwa kwehadiwe kwemisebenzi ye-athomu (i-Hardware Atomics) sekuqalisiwe.
- I-FPU isiphinde yaklanywa kabusha ngokuphelele futhi sekufakwe amabhlogo amasha okuphindaphinda (i-Wallace-tree, i-Folded-radix) kanye ne-adder (i-Kogge-Stone).
- Kungezwe i-virtual memory stack esekelwe kuyunithi yokuphatha imemori (i-MMU) ngokusekelwa kokwakhiwa kwekheli le-32-bit SV32 virtual.
- Ukusekelwa kwesandiso se-RISC-V Zicond ngokuqaliswa kwemisebenzi enemibandela.
- I-washi elihlanganisiwe elihlanganisiwe.
- Ukusekelwa kolimi lwe-HIP (Heterogeneous Interface for Portability) kusetshenziswe ngohlaka lwe-chipStar, oluhumusha i-HIP ibe yi-SPIR-V.
- Ukuhlanganiswa okugcwele nesilingisi se-GEM5 sekuhlinzekiwe, futhi ukwesekwa kwesilingisi se-SimX kusakhiwo se-TLM (Transaction-Level Modeling) kungeziwe.
- Kungezwe ukwesekwa kwamathuluzi e-Synopsys kanye ne-Yosys okwenziwa kwe-logic ekukhiqizweni kwama-chip, kanye nokusekelwa kokusebenzisa imitapo yolwazi ye-ASAP7 (7nm), SAED14 (14nm), kanye ne-NanGate (15nm) ejwayelekile.
- I-toolchain yokubhekisela ibuyekeziwe yaba yi-LLVM 20 kanye ne-POCL 7.0.
Source: opennet.ru
