Rambus presented a set of solutions for the release of products with PCIe 5.0 interface

The industry is moving at full speed towards the practical implementation of the next PCI Express interface. This time in version 5.0 with a transfer rate of 32 gigatransactions per second per line. It stalled for so long during the transition to the PCIe 4.0 bus that now, just a year after the release of the final PCIe 5.0 specifications, it is seeking to enter the commercial space. Why such a rush? Adherents argue that further development of AI and IoT is impossible without a doubling or even greater expansion of the bandwidth between processors and accelerators.

Not long ago we told you that Astera Labs, Synopsys and Intel at a specialized conference in Taipei showed The first comprehensive solution to prepare for the release of PCIe 5.0 products. The demonstration used a “hodgepodge” of an Intel controller, a Synopsys physical layer and Astera Labs retimers. Getting all this from one developer (though, apparently, without retimers that restore signal integrity) became possible thanks to the efforts of the well-known company Rambus.

Rambus is known not only for its squabbles in the world of patent law over interface designs, but also for its design of signal structures for memory controllers and data buses. More recently Rambus showed a working solution for creating GDDR6 memory controllers with a bandwidth of 18 Gbit/s per line. And today Rambus suggested a set of solutions for releasing products with PCIe 5.0 interface.

The kit can be immediately licensed by those wishing to purchase it as a whole or individually for integration into third-party products using the PCI Express 5.0 bus. The kit includes a PCIe 5.0 controller developed by the company recently acquired by Rambus Northwest Logic and a proprietary Rambus physical layer (PHY) for the PCIe 5.0 interface. The kit guarantees backward compatibility with previous PCIe specifications and is optimized for production as part of SoCs and controllers using the 7nm process technology and FinFET transistors.

Rambus, as the owner and supplier of a single solution, guarantees comprehensive support for developers and promises the fastest time to market for products supporting the PCIe 5.0 bus. Finally, Rambus reports that the presented physical layer is fully compatible and can be used for the latest interprocessor interface Compute Express Link, and this is an entry into the operational space in the niche of supercomputers.

Source: 3dnews.ru