CoreBoot 25.09, a project developing a free alternative to proprietary firmware and BIOS, has been released. The project's code is distributed under the GPLv2 license. The new version includes 684 changes, developed with the help of 110 developers.
Major changes:
- Support for motherboards has been implemented:
- ASROCK SPC741D8-2L2T/BCM.
- GIGABYTE GA_H81M_D2W.
- HP 260 G1 DM, HP Compaq Pro 6300 SFF/MT, HP ProDesk 600 G1 SFF.
- Intel Ptlrvp4es
- Lenovo ThinkPad T480/T480s.
- 11 boards used in various devices running Chrome OS or серверах Google.
- SPI Flash and payload component loading has been significantly accelerated. When building in CONFIG_SSE mode, the LZMA-based decompression code utilizes SSE prefetch instructions, enabling data to be preemptively loaded into the CPU cache without interrupting the decompression operation. Testing the 100 Mbit/s SPI interface on mobile Intel Sandy Bridge CPUs resulted in a 46 ms reduction in load time and a 30% acceleration in payload component decompression.
Asynchronous file loading support has been implemented for Intel Panther Lake platforms, using SPI DMA to preemptively load the fsps.bin file in parallel with other CPU tasks. On Fatcat devices, this optimization improved loading times by 17-18 ms. DMA operation efficiency has been improved. A new synchronization function, cbfs_preload_wait_for_all(), has been added, allowing asynchronous operations to safely complete before deactivating storage backends. The Fast SPI DMA subsystem implements a token-based data transfer queue, minimizing delays between successive DMA operations and ensuring more predictable loading performance.
- Boot mode detection has been implemented, allowing platforms to communicate critical boot state information to payload components. Detection of normal boot mode, low battery mode, and charging battery mode is supported via the standardized boot_mode_t interface.
- The MTRR (Memory Type Range Registers) control for video memory has been redesigned, reducing the initialization time of the FSP-S (Firmware Support Package - Silicon) by moving the MTRR WC (Write-Combine) setting for video memory from the logo rendering functions to the chip initialization stage. As a result, the graphics subsystem initialization time has been reduced from 123 to 115 ms. The redesign also simplified code maintenance by separating MTRR control from the logo rendering functions.
- The amdfwtool utility, designed for working with AMD firmware, has improved addressing mode processing and expanded capabilities for parsing the EFW structure on the Turin platform.
- The smmstoretool utility has been updated to support variable block sizes and GUID partition table aliasing in Secure Boot mode to improve management of UEFI variables.
- Expanded TPM support for various platforms with CRB TPM and improved fTPM integration for AMD platforms.
- Improved logo rendering.
- Improved compatibility with Bochs display driver.
- Improved stability of the cbfstool utility when sorting the FIT table and in case of failures during compression operations.
- Changes have been made to improve power management, memory initialization, and hardware interface support for Intel, AMD, MediaTek, and Qualcomm platforms.
- Updated versions of binutils 2.44, ACPICA 20250404, MPFR 4.2.2, SeaBIOS 1.17.0, U-Boot 2025.07.
Source: opennet.ru
