In 2022, Ventana Micro Systems announced the first truly server RISC-V processors, Veyron V1. The announcement of chips that promise to compete on equal terms with the best x86 processors with x86 architecture sounded loud. However, the Veyron V1 did not gain popularity, but recently the company announced the second generation of Veyron V2 chips, which more fully embodied the principles of modular design and received a number of improvements. As in the first generation, the development company continues to adhere to the concept of a βprocessor-designerβ with a chiplet design. At the center of the 4nm Veyron V2 is still the I/O hub based on AMBA CHI, covering memory controllers and PCI Express buses, as well as IOMMU and AIA blocks. Computing chiplets are connected to it via the UCIe interface. UCIe connection latency is less than 7 ns.
Source: 3dnews.ru